Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	24948937	15412	0	0
attest_sw_binding_0_rd_A	24948937	2703	0	0
attest_sw_binding_1_rd_A	24948937	2745	0	0
attest_sw_binding_2_rd_A	24948937	2697	0	0
attest_sw_binding_3_rd_A	24948937	2660	0	0
attest_sw_binding_4_rd_A	24948937	2902	0	0
attest_sw_binding_5_rd_A	24948937	2687	0	0
attest_sw_binding_6_rd_A	24948937	2614	0	0
attest_sw_binding_7_rd_A	24948937	2860	0	0
intr_enable_rd_A	24948937	3300	0	0
key_version_rd_A	24948937	2764	0	0
max_creator_key_ver_regwen_rd_A	24948937	2718	0	0
max_owner_int_key_ver_regwen_rd_A	24948937	2647	0	0
max_owner_key_ver_regwen_rd_A	24948937	2704	0	0
reseed_interval_regwen_rd_A	24948937	2687	0	0
salt_0_rd_A	24948937	2563	0	0
salt_1_rd_A	24948937	2593	0	0
salt_2_rd_A	24948937	2798	0	0
salt_3_rd_A	24948937	2547	0	0
salt_4_rd_A	24948937	2750	0	0
salt_5_rd_A	24948937	2717	0	0
salt_6_rd_A	24948937	2836	0	0
salt_7_rd_A	24948937	2708	0	0
sealing_sw_binding_0_rd_A	24948937	2778	0	0
sealing_sw_binding_1_rd_A	24948937	2594	0	0
sealing_sw_binding_2_rd_A	24948937	2753	0	0
sealing_sw_binding_3_rd_A	24948937	2827	0	0
sealing_sw_binding_4_rd_A	24948937	2761	0	0
sealing_sw_binding_5_rd_A	24948937	2663	0	0
sealing_sw_binding_6_rd_A	24948937	2732	0	0
sealing_sw_binding_7_rd_A	24948937	2635	0	0
sideload_clear_rd_A	24948937	2725	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24948937	15412	0	0
T6	0	1127	0	0
T47	4116	0	0	0
T50	2521	0	0	0
T56	10539	0	0	0
T96	8919	414	0	0
T111	0	524	0	0
T124	0	58	0	0
T125	0	172	0	0
T126	0	576	0	0
T127	0	372	0	0
T128	0	41	0	0
T129	0	60	0	0
T130	0	240	0	0
T131	4490	0	0	0
T132	6941	0	0	0
T133	5674	0	0	0
T134	11296	0	0	0
T135	3907	0	0	0
T136	6885	0	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24948937	2703	0	0
T62	84151	0	0	0
T84	3755	0	0	0
T124	35187	29	0	0
T128	0	27	0	0
T148	0	7	0	0
T152	0	244	0	0
T154	0	47	0	0
T158	0	68	0	0
T174	0	35	0	0
T175	0	79	0	0
T176	0	4	0	0
T177	0	9	0	0
T178	10074	0	0	0
T179	4945	0	0	0
T180	4950	0	0	0
T181	7181	0	0	0
T182	5758	0	0	0
T183	9452	0	0	0
T184	9564	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24948937	2745	0	0
T62	84151	0	0	0
T84	3755	0	0	0
T124	35187	35	0	0
T128	0	30	0	0
T148	0	13	0	0
T152	0	262	0	0
T154	0	29	0	0
T158	0	108	0	0
T174	0	26	0	0
T175	0	67	0	0
T176	0	1	0	0
T177	0	30	0	0
T178	10074	0	0	0
T179	4945	0	0	0
T180	4950	0	0	0
T181	7181	0	0	0
T182	5758	0	0	0
T183	9452	0	0	0
T184	9564	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24948937	2697	0	0
T62	84151	0	0	0
T84	3755	0	0	0
T124	35187	32	0	0
T128	0	23	0	0
T148	0	6	0	0
T152	0	313	0	0
T154	0	48	0	0
T158	0	41	0	0
T174	0	22	0	0
T175	0	71	0	0
T176	0	12	0	0
T177	0	26	0	0
T178	10074	0	0	0
T179	4945	0	0	0
T180	4950	0	0	0
T181	7181	0	0	0
T182	5758	0	0	0
T183	9452	0	0	0
T184	9564	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24948937	2660	0	0
T62	84151	0	0	0
T84	3755	0	0	0
T124	35187	38	0	0
T128	0	33	0	0
T148	0	5	0	0
T152	0	251	0	0
T154	0	44	0	0
T158	0	73	0	0
T174	0	35	0	0
T175	0	82	0	0
T176	0	8	0	0
T177	0	11	0	0
T178	10074	0	0	0
T179	4945	0	0	0
T180	4950	0	0	0
T181	7181	0	0	0
T182	5758	0	0	0
T183	9452	0	0	0
T184	9564	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24948937	2902	0	0
T62	84151	0	0	0
T84	3755	0	0	0
T124	35187	25	0	0
T128	0	30	0	0
T148	0	1	0	0
T152	0	300	0	0
T154	0	29	0	0
T158	0	64	0	0
T174	0	33	0	0
T175	0	88	0	0
T176	0	7	0	0
T177	0	21	0	0
T178	10074	0	0	0
T179	4945	0	0	0
T180	4950	0	0	0
T181	7181	0	0	0
T182	5758	0	0	0
T183	9452	0	0	0
T184	9564	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24948937	2687	0	0
T62	84151	0	0	0
T84	3755	0	0	0
T124	35187	54	0	0
T128	0	41	0	0
T148	0	11	0	0
T152	0	258	0	0
T154	0	38	0	0
T158	0	92	0	0
T174	0	28	0	0
T175	0	81	0	0
T176	0	8	0	0
T177	0	12	0	0
T178	10074	0	0	0
T179	4945	0	0	0
T180	4950	0	0	0
T181	7181	0	0	0
T182	5758	0	0	0
T183	9452	0	0	0
T184	9564	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24948937	2614	0	0
T62	84151	0	0	0
T84	3755	0	0	0
T124	35187	23	0	0
T128	0	21	0	0
T148	0	8	0	0
T152	0	258	0	0
T154	0	41	0	0
T158	0	92	0	0
T174	0	24	0	0
T175	0	49	0	0
T176	0	2	0	0
T177	0	24	0	0
T178	10074	0	0	0
T179	4945	0	0	0
T180	4950	0	0	0
T181	7181	0	0	0
T182	5758	0	0	0
T183	9452	0	0	0
T184	9564	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24948937	2860	0	0
T62	84151	0	0	0
T84	3755	0	0	0
T124	35187	39	0	0
T128	0	25	0	0
T148	0	13	0	0
T152	0	269	0	0
T154	0	38	0	0
T158	0	80	0	0
T174	0	19	0	0
T175	0	86	0	0
T176	0	2	0	0
T177	0	12	0	0
T178	10074	0	0	0
T179	4945	0	0	0
T180	4950	0	0	0
T181	7181	0	0	0
T182	5758	0	0	0
T183	9452	0	0	0
T184	9564	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24948937	3300	0	0
T5	0	39	0	0
T7	0	10	0	0
T18	145719	24	0	0
T19	22846	0	0	0
T33	10595	0	0	0
T34	5853	0	0	0
T36	14771	0	0	0
T44	2326	0	0	0
T48	0	53	0	0
T49	4677	0	0	0
T55	14141	0	0	0
T62	0	20	0	0
T78	16609	0	0	0
T79	5462	0	0	0
T124	0	31	0	0
T128	0	43	0	0
T185	0	16	0	0
T186	0	43	0	0
T187	0	19	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24948937	2764	0	0
T62	84151	0	0	0
T84	3755	0	0	0
T124	35187	24	0	0
T128	0	31	0	0
T148	0	15	0	0
T152	0	306	0	0
T154	0	45	0	0
T158	0	64	0	0
T174	0	28	0	0
T175	0	62	0	0
T176	0	9	0	0
T177	0	11	0	0
T178	10074	0	0	0
T179	4945	0	0	0
T180	4950	0	0	0
T181	7181	0	0	0
T182	5758	0	0	0
T183	9452	0	0	0
T184	9564	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24948937	2718	0	0
T62	84151	0	0	0
T84	3755	0	0	0
T124	35187	40	0	0
T128	0	24	0	0
T148	0	12	0	0
T152	0	302	0	0
T154	0	52	0	0
T158	0	79	0	0
T174	0	28	0	0
T175	0	46	0	0
T176	0	10	0	0
T177	0	5	0	0
T178	10074	0	0	0
T179	4945	0	0	0
T180	4950	0	0	0
T181	7181	0	0	0
T182	5758	0	0	0
T183	9452	0	0	0
T184	9564	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24948937	2647	0	0
T62	84151	0	0	0
T84	3755	0	0	0
T124	35187	30	0	0
T128	0	28	0	0
T148	0	12	0	0
T152	0	264	0	0
T154	0	29	0	0
T158	0	83	0	0
T174	0	24	0	0
T175	0	84	0	0
T176	0	8	0	0
T177	0	7	0	0
T178	10074	0	0	0
T179	4945	0	0	0
T180	4950	0	0	0
T181	7181	0	0	0
T182	5758	0	0	0
T183	9452	0	0	0
T184	9564	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24948937	2704	0	0
T62	84151	0	0	0
T84	3755	0	0	0
T124	35187	23	0	0
T128	0	32	0	0
T148	0	11	0	0
T152	0	305	0	0
T154	0	54	0	0
T158	0	75	0	0
T174	0	41	0	0
T175	0	69	0	0
T176	0	4	0	0
T177	0	16	0	0
T178	10074	0	0	0
T179	4945	0	0	0
T180	4950	0	0	0
T181	7181	0	0	0
T182	5758	0	0	0
T183	9452	0	0	0
T184	9564	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24948937	2687	0	0
T62	84151	0	0	0
T84	3755	0	0	0
T124	35187	31	0	0
T128	0	37	0	0
T148	0	5	0	0
T152	0	249	0	0
T154	0	48	0	0
T174	0	39	0	0
T175	0	80	0	0
T176	0	3	0	0
T177	0	20	0	0
T178	10074	0	0	0
T179	4945	0	0	0
T180	4950	0	0	0
T181	7181	0	0	0
T182	5758	0	0	0
T183	9452	0	0	0
T184	9564	0	0	0
T188	0	1	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24948937	2563	0	0
T62	84151	0	0	0
T84	3755	0	0	0
T124	35187	24	0	0
T128	0	46	0	0
T148	0	15	0	0
T152	0	211	0	0
T154	0	33	0	0
T158	0	80	0	0
T174	0	29	0	0
T175	0	63	0	0
T176	0	6	0	0
T177	0	17	0	0
T178	10074	0	0	0
T179	4945	0	0	0
T180	4950	0	0	0
T181	7181	0	0	0
T182	5758	0	0	0
T183	9452	0	0	0
T184	9564	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24948937	2593	0	0
T62	84151	0	0	0
T84	3755	0	0	0
T124	35187	32	0	0
T128	0	30	0	0
T148	0	8	0	0
T152	0	258	0	0
T154	0	50	0	0
T158	0	89	0	0
T174	0	13	0	0
T175	0	57	0	0
T176	0	11	0	0
T177	0	25	0	0
T178	10074	0	0	0
T179	4945	0	0	0
T180	4950	0	0	0
T181	7181	0	0	0
T182	5758	0	0	0
T183	9452	0	0	0
T184	9564	0	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24948937	2798	0	0
T62	84151	0	0	0
T84	3755	0	0	0
T124	35187	35	0	0
T128	0	24	0	0
T148	0	10	0	0
T152	0	262	0	0
T154	0	59	0	0
T158	0	75	0	0
T174	0	34	0	0
T175	0	75	0	0
T176	0	8	0	0
T177	0	16	0	0
T178	10074	0	0	0
T179	4945	0	0	0
T180	4950	0	0	0
T181	7181	0	0	0
T182	5758	0	0	0
T183	9452	0	0	0
T184	9564	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24948937	2547	0	0
T62	84151	0	0	0
T84	3755	0	0	0
T124	35187	20	0	0
T128	0	27	0	0
T148	0	2	0	0
T152	0	252	0	0
T154	0	35	0	0
T158	0	82	0	0
T174	0	27	0	0
T175	0	58	0	0
T176	0	8	0	0
T177	0	12	0	0
T178	10074	0	0	0
T179	4945	0	0	0
T180	4950	0	0	0
T181	7181	0	0	0
T182	5758	0	0	0
T183	9452	0	0	0
T184	9564	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24948937	2750	0	0
T62	84151	0	0	0
T84	3755	0	0	0
T124	35187	37	0	0
T128	0	52	0	0
T148	0	8	0	0
T152	0	285	0	0
T154	0	48	0	0
T158	0	74	0	0
T174	0	27	0	0
T175	0	58	0	0
T176	0	11	0	0
T177	0	14	0	0
T178	10074	0	0	0
T179	4945	0	0	0
T180	4950	0	0	0
T181	7181	0	0	0
T182	5758	0	0	0
T183	9452	0	0	0
T184	9564	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24948937	2717	0	0
T62	84151	0	0	0
T84	3755	0	0	0
T124	35187	37	0	0
T128	0	29	0	0
T148	0	8	0	0
T152	0	269	0	0
T154	0	49	0	0
T158	0	77	0	0
T174	0	22	0	0
T175	0	45	0	0
T176	0	13	0	0
T177	0	14	0	0
T178	10074	0	0	0
T179	4945	0	0	0
T180	4950	0	0	0
T181	7181	0	0	0
T182	5758	0	0	0
T183	9452	0	0	0
T184	9564	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24948937	2836	0	0
T62	84151	0	0	0
T84	3755	0	0	0
T124	35187	50	0	0
T128	0	31	0	0
T148	0	15	0	0
T152	0	267	0	0
T154	0	55	0	0
T158	0	90	0	0
T174	0	19	0	0
T175	0	74	0	0
T176	0	9	0	0
T177	0	8	0	0
T178	10074	0	0	0
T179	4945	0	0	0
T180	4950	0	0	0
T181	7181	0	0	0
T182	5758	0	0	0
T183	9452	0	0	0
T184	9564	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24948937	2708	0	0
T62	84151	0	0	0
T84	3755	0	0	0
T124	35187	23	0	0
T128	0	34	0	0
T148	0	7	0	0
T152	0	287	0	0
T154	0	44	0	0
T158	0	73	0	0
T174	0	20	0	0
T175	0	79	0	0
T176	0	2	0	0
T177	0	10	0	0
T178	10074	0	0	0
T179	4945	0	0	0
T180	4950	0	0	0
T181	7181	0	0	0
T182	5758	0	0	0
T183	9452	0	0	0
T184	9564	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24948937	2778	0	0
T62	84151	0	0	0
T84	3755	0	0	0
T124	35187	46	0	0
T128	0	43	0	0
T148	0	10	0	0
T152	0	248	0	0
T154	0	39	0	0
T158	0	90	0	0
T174	0	22	0	0
T175	0	82	0	0
T176	0	14	0	0
T177	0	22	0	0
T178	10074	0	0	0
T179	4945	0	0	0
T180	4950	0	0	0
T181	7181	0	0	0
T182	5758	0	0	0
T183	9452	0	0	0
T184	9564	0	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24948937	2594	0	0
T62	84151	0	0	0
T84	3755	0	0	0
T124	35187	25	0	0
T128	0	22	0	0
T148	0	8	0	0
T152	0	246	0	0
T154	0	40	0	0
T158	0	100	0	0
T174	0	33	0	0
T175	0	64	0	0
T176	0	1	0	0
T177	0	17	0	0
T178	10074	0	0	0
T179	4945	0	0	0
T180	4950	0	0	0
T181	7181	0	0	0
T182	5758	0	0	0
T183	9452	0	0	0
T184	9564	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24948937	2753	0	0
T62	84151	0	0	0
T84	3755	0	0	0
T124	35187	16	0	0
T128	0	12	0	0
T148	0	7	0	0
T152	0	272	0	0
T154	0	30	0	0
T158	0	74	0	0
T174	0	43	0	0
T175	0	86	0	0
T176	0	14	0	0
T177	0	30	0	0
T178	10074	0	0	0
T179	4945	0	0	0
T180	4950	0	0	0
T181	7181	0	0	0
T182	5758	0	0	0
T183	9452	0	0	0
T184	9564	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24948937	2827	0	0
T62	84151	0	0	0
T84	3755	0	0	0
T124	35187	25	0	0
T128	0	51	0	0
T148	0	9	0	0
T152	0	279	0	0
T154	0	46	0	0
T158	0	85	0	0
T174	0	25	0	0
T175	0	65	0	0
T176	0	9	0	0
T177	0	16	0	0
T178	10074	0	0	0
T179	4945	0	0	0
T180	4950	0	0	0
T181	7181	0	0	0
T182	5758	0	0	0
T183	9452	0	0	0
T184	9564	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24948937	2761	0	0
T62	84151	0	0	0
T84	3755	0	0	0
T124	35187	31	0	0
T128	0	31	0	0
T148	0	7	0	0
T152	0	315	0	0
T154	0	42	0	0
T158	0	75	0	0
T174	0	14	0	0
T175	0	52	0	0
T176	0	15	0	0
T177	0	19	0	0
T178	10074	0	0	0
T179	4945	0	0	0
T180	4950	0	0	0
T181	7181	0	0	0
T182	5758	0	0	0
T183	9452	0	0	0
T184	9564	0	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24948937	2663	0	0
T62	84151	0	0	0
T84	3755	0	0	0
T124	35187	31	0	0
T128	0	17	0	0
T148	0	5	0	0
T152	0	224	0	0
T154	0	39	0	0
T158	0	97	0	0
T174	0	20	0	0
T175	0	74	0	0
T176	0	10	0	0
T177	0	13	0	0
T178	10074	0	0	0
T179	4945	0	0	0
T180	4950	0	0	0
T181	7181	0	0	0
T182	5758	0	0	0
T183	9452	0	0	0
T184	9564	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24948937	2732	0	0
T62	84151	0	0	0
T84	3755	0	0	0
T124	35187	33	0	0
T128	0	26	0	0
T148	0	12	0	0
T152	0	248	0	0
T154	0	36	0	0
T158	0	74	0	0
T174	0	15	0	0
T175	0	70	0	0
T176	0	5	0	0
T177	0	21	0	0
T178	10074	0	0	0
T179	4945	0	0	0
T180	4950	0	0	0
T181	7181	0	0	0
T182	5758	0	0	0
T183	9452	0	0	0
T184	9564	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24948937	2635	0	0
T62	84151	0	0	0
T84	3755	0	0	0
T124	35187	35	0	0
T128	0	32	0	0
T148	0	1	0	0
T152	0	254	0	0
T154	0	32	0	0
T158	0	94	0	0
T174	0	14	0	0
T175	0	66	0	0
T176	0	8	0	0
T177	0	24	0	0
T178	10074	0	0	0
T179	4945	0	0	0
T180	4950	0	0	0
T181	7181	0	0	0
T182	5758	0	0	0
T183	9452	0	0	0
T184	9564	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24948937	2725	0	0
T62	84151	0	0	0
T84	3755	0	0	0
T124	35187	52	0	0
T128	0	59	0	0
T148	0	7	0	0
T152	0	274	0	0
T154	0	27	0	0
T158	0	91	0	0
T174	0	20	0	0
T175	0	56	0	0
T176	0	2	0	0
T177	0	14	0	0
T178	10074	0	0	0
T179	4945	0	0	0
T180	4950	0	0	0
T181	7181	0	0	0
T182	5758	0	0	0
T183	9452	0	0	0
T184	9564	0	0	0