Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3438326	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

598185

1

T1

754

T2

222

T3

17

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3632677	1			T1	960		T2	1396		T3	1052
values[0x0]	200412	1			T1	257		T2	65		T3	9
values[0x1]	203422	1			T1	270		T2	68		T3	12

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2349766	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1686745

1

T1

914

T2

619

T3

336

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11509	1			T1	4		T2	4		T3	8
valid_sources[0x01]	21245	1			T1	8		T3	8		T15	2
valid_sources[0x02]	37109	1			T1	6		T2	2		T3	2
valid_sources[0x03]	11466	1			T1	6		T2	2		T3	11
valid_sources[0x04]	11655	1			T1	4		T3	8		T15	16
valid_sources[0x05]	11796	1			T1	6		T2	4		T3	9
valid_sources[0x06]	12439	1			T1	7		T2	6		T3	3
valid_sources[0x07]	12279	1			T1	2		T2	5		T3	2
valid_sources[0x08]	14708	1			T1	4		T2	9		T3	8
valid_sources[0x09]	12884	1			T1	11		T2	9		T3	7
valid_sources[0x0a]	12462	1			T1	9		T2	10		T3	2
valid_sources[0x0b]	12054	1			T1	6		T2	8		T3	1
valid_sources[0x0c]	18138	1			T1	4		T2	16		T3	7
valid_sources[0x0d]	11390	1			T1	11		T2	1		T3	3
valid_sources[0x0e]	11361	1			T1	9		T2	13		T3	3
valid_sources[0x0f]	11369	1			T1	6		T2	10		T3	6
valid_sources[0x10]	11621	1			T1	6		T2	1		T3	1
valid_sources[0x11]	11847	1			T1	7		T2	16		T3	2
valid_sources[0x12]	11963	1			T1	3		T2	5		T3	2
valid_sources[0x13]	12608	1			T1	10		T2	8		T3	2
valid_sources[0x14]	12593	1			T1	4		T2	10		T3	2
valid_sources[0x15]	12023	1			T1	3		T2	6		T3	5
valid_sources[0x16]	11611	1			T1	3		T2	4		T3	8
valid_sources[0x17]	12896	1			T1	10		T2	4		T3	7
valid_sources[0x18]	27062	1			T1	6		T2	3		T3	4
valid_sources[0x19]	13104	1			T1	6		T2	15		T3	9
valid_sources[0x1a]	11589	1			T1	3		T2	2		T15	7
valid_sources[0x1b]	19630	1			T1	3		T2	5		T15	17
valid_sources[0x1c]	11854	1			T1	10		T2	5		T3	4
valid_sources[0x1d]	12176	1			T1	6		T2	2		T3	2
valid_sources[0x1e]	11523	1			T1	4		T2	3		T3	3
valid_sources[0x1f]	15649	1			T1	4		T2	9		T3	2
valid_sources[0x20]	14397	1			T1	5		T2	5		T3	2
valid_sources[0x21]	11728	1			T1	4		T2	17		T3	6
valid_sources[0x22]	12447	1			T1	5		T2	5		T3	4
valid_sources[0x23]	11895	1			T1	7		T2	12		T3	2
valid_sources[0x24]	12626	1			T1	5		T2	7		T3	7
valid_sources[0x25]	11571	1			T1	3		T3	8		T15	14
valid_sources[0x26]	11972	1			T1	9		T2	4		T15	1
valid_sources[0x27]	12746	1			T1	3		T3	6		T15	12
valid_sources[0x28]	12190	1			T1	4		T2	3		T3	7
valid_sources[0x29]	12191	1			T1	12		T2	4		T3	4
valid_sources[0x2a]	11677	1			T1	6		T2	3		T3	4
valid_sources[0x2b]	11719	1			T1	8		T2	5		T3	7
valid_sources[0x2c]	13472	1			T1	8		T2	9		T3	1
valid_sources[0x2d]	11936	1			T1	6		T2	18		T3	7
valid_sources[0x2e]	12436	1			T1	4		T2	7		T3	7
valid_sources[0x2f]	11545	1			T1	8		T2	3		T3	3
valid_sources[0x30]	12238	1			T1	6		T2	1		T3	2
valid_sources[0x31]	11296	1			T1	7		T2	3		T3	1
valid_sources[0x32]	11323	1			T1	6		T2	3		T3	3
valid_sources[0x33]	11695	1			T1	5		T2	9		T3	4
valid_sources[0x34]	24531	1			T1	4		T2	1		T3	5
valid_sources[0x35]	12344	1			T1	8		T2	2		T3	1
valid_sources[0x36]	12822	1			T1	11		T2	1		T3	1
valid_sources[0x37]	12310	1			T1	8		T2	9		T3	2
valid_sources[0x38]	17885	1			T1	7		T2	5		T3	11
valid_sources[0x39]	11564	1			T1	5		T2	17		T3	5
valid_sources[0x3a]	11685	1			T2	2		T3	8		T15	1
valid_sources[0x3b]	15648	1			T1	5		T2	8		T15	8
valid_sources[0x3c]	11164	1			T1	7		T2	9		T3	1
valid_sources[0x3d]	11551	1			T1	3		T2	4		T3	6
valid_sources[0x3e]	14671	1			T1	5		T3	1		T15	18
valid_sources[0x3f]	11828	1			T1	6		T2	5		T3	5
valid_sources[0x40]	13637	1			T1	1		T2	7		T3	5
valid_sources[0x41]	16740	1			T1	10		T2	8		T3	4
valid_sources[0x42]	11391	1			T1	8		T2	9		T3	3
valid_sources[0x43]	12656	1			T1	10		T3	4		T15	8
valid_sources[0x44]	12158	1			T1	6		T2	6		T3	1
valid_sources[0x45]	12992	1			T1	6		T2	2		T3	4
valid_sources[0x46]	18243	1			T1	6		T2	9		T3	3
valid_sources[0x47]	11919	1			T1	3		T2	1		T3	6
valid_sources[0x48]	11747	1			T1	7		T2	1		T3	1
valid_sources[0x49]	14184	1			T1	3		T2	4		T3	4
valid_sources[0x4a]	12534	1			T1	8		T2	16		T3	4
valid_sources[0x4b]	16432	1			T1	9		T2	6		T3	5
valid_sources[0x4c]	14898	1			T1	1		T3	5		T15	2
valid_sources[0x4d]	11325	1			T1	5		T3	2		T15	11
valid_sources[0x4e]	11565	1			T1	8		T2	4		T3	4
valid_sources[0x4f]	12549	1			T1	10		T2	1		T3	6
valid_sources[0x50]	12444	1			T1	9		T2	2		T3	9
valid_sources[0x51]	15100	1			T1	5		T2	1		T3	2
valid_sources[0x52]	11145	1			T1	6		T2	3		T3	1
valid_sources[0x53]	11069	1			T1	6		T2	6		T3	4
valid_sources[0x54]	32907	1			T1	7		T2	1		T3	7
valid_sources[0x55]	12260	1			T1	9		T2	4		T3	3
valid_sources[0x56]	17600	1			T1	8		T2	3		T3	3
valid_sources[0x57]	15636	1			T1	6		T2	6		T3	2
valid_sources[0x58]	11379	1			T1	6		T2	8		T3	2
valid_sources[0x59]	11411	1			T1	4		T3	7		T15	12
valid_sources[0x5a]	12016	1			T1	8		T2	15		T3	6
valid_sources[0x5b]	13121	1			T1	2		T15	22		T16	12
valid_sources[0x5c]	11877	1			T1	5		T3	9		T15	2
valid_sources[0x5d]	11618	1			T1	12		T3	7		T15	8
valid_sources[0x5e]	11705	1			T1	4		T3	5		T15	6
valid_sources[0x5f]	11533	1			T1	4		T2	3		T3	4
valid_sources[0x60]	13687	1			T1	10		T2	2		T3	4
valid_sources[0x61]	12182	1			T1	2		T2	4		T3	6
valid_sources[0x62]	13135	1			T1	8		T2	5		T3	4
valid_sources[0x63]	11701	1			T1	3		T2	12		T3	5
valid_sources[0x64]	16829	1			T1	3		T2	12		T3	1
valid_sources[0x65]	11879	1			T1	5		T2	6		T3	1
valid_sources[0x66]	11697	1			T1	7		T2	11		T3	5
valid_sources[0x67]	30867	1			T1	2		T3	3		T15	9
valid_sources[0x68]	11924	1			T1	7		T2	14		T3	7
valid_sources[0x69]	10805	1			T1	8		T2	7		T3	3
valid_sources[0x6a]	13919	1			T1	2		T2	3		T3	4
valid_sources[0x6b]	14795	1			T1	5		T2	7		T3	7
valid_sources[0x6c]	28030	1			T1	12		T2	7		T3	4
valid_sources[0x6d]	11636	1			T1	8		T2	7		T3	1
valid_sources[0x6e]	12567	1			T1	2		T2	2		T3	2
valid_sources[0x6f]	12037	1			T1	10		T2	11		T3	7
valid_sources[0x70]	11165	1			T1	5		T2	20		T3	1
valid_sources[0x71]	18669	1			T1	3		T2	11		T3	4
valid_sources[0x72]	11772	1			T1	6		T2	1		T3	4
valid_sources[0x73]	13609	1			T1	5		T2	3		T3	9
valid_sources[0x74]	15056	1			T1	7		T2	4		T3	2
valid_sources[0x75]	11209	1			T1	7		T2	3		T3	1
valid_sources[0x76]	11666	1			T1	4		T2	25		T3	4
valid_sources[0x77]	11468	1			T1	9		T2	5		T3	9
valid_sources[0x78]	12214	1			T1	5		T2	6		T3	2
valid_sources[0x79]	11465	1			T1	5		T2	6		T3	2
valid_sources[0x7a]	11259	1			T1	6		T2	16		T3	3
valid_sources[0x7b]	12396	1			T1	5		T15	2		T16	10
valid_sources[0x7c]	13173	1			T1	4		T2	1		T3	2
valid_sources[0x7d]	11943	1			T1	3		T2	2		T3	10
valid_sources[0x7e]	36797	1			T1	3		T2	10		T3	3
valid_sources[0x7f]	12187	1			T1	10		T2	7		T3	4
valid_sources[0x80]	12492	1			T1	9		T3	7		T15	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

324283

1

T1

414

T2

183

T3

8

values[0x0]

all_enables

biggest_size

144119

1

T1

169

T2

23

T3

4

values[0x1]

all_enables

biggest_size

129783

1

T1

171

T2

16

T3

5