Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3268427	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

619359

1

T1

27

T2

372

T3

299

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3473387	1			T1	909		T2	965		T3	567
values[0x0]	206477	1			T1	17		T2	145		T3	99
values[0x1]	207922	1			T1	17		T2	133		T3	105

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2237565	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1650221

1

T1

323

T2

623

T3

435

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12651	1			T2	4		T13	3		T14	4
valid_sources[0x01]	13203	1			T2	1		T3	4		T13	2
valid_sources[0x02]	13045	1			T3	17		T13	5		T18	6
valid_sources[0x03]	12972	1			T13	2		T15	4		T18	6
valid_sources[0x04]	12211	1			T2	2		T3	1		T13	4
valid_sources[0x05]	15425	1			T2	3		T3	6		T13	5
valid_sources[0x06]	14790	1			T2	4		T3	3		T13	2
valid_sources[0x07]	20341	1			T2	2		T13	3		T14	7
valid_sources[0x08]	17069	1			T2	11		T13	1		T14	3
valid_sources[0x09]	16142	1			T2	2		T3	2		T13	2
valid_sources[0x0a]	18070	1			T2	1		T13	4		T14	4
valid_sources[0x0b]	12703	1			T2	2		T3	3		T13	1
valid_sources[0x0c]	12818	1			T2	3		T3	3		T13	4
valid_sources[0x0d]	17034	1			T2	2		T13	3		T14	2
valid_sources[0x0e]	13781	1			T2	7		T13	4		T14	2
valid_sources[0x0f]	13835	1			T2	16		T13	1		T14	3
valid_sources[0x10]	12571	1			T2	2		T13	1		T14	1
valid_sources[0x11]	14112	1			T2	3		T3	4		T13	1
valid_sources[0x12]	12509	1			T2	2		T13	2		T14	1
valid_sources[0x13]	16428	1			T2	6		T3	8		T13	3
valid_sources[0x14]	12296	1			T2	2		T13	3		T14	3
valid_sources[0x15]	12969	1			T2	11		T3	2		T13	2
valid_sources[0x16]	12674	1			T2	11		T13	2		T14	1
valid_sources[0x17]	13579	1			T2	3		T3	4		T13	2
valid_sources[0x18]	12903	1			T2	10		T3	4		T13	4
valid_sources[0x19]	12950	1			T2	1		T3	3		T13	1
valid_sources[0x1a]	15407	1			T2	3		T3	4		T13	2
valid_sources[0x1b]	44879	1			T2	2		T13	1		T15	4
valid_sources[0x1c]	12855	1			T2	4		T3	4		T13	4
valid_sources[0x1d]	14807	1			T2	10		T3	1		T13	1
valid_sources[0x1e]	13981	1			T2	20		T15	1		T16	1
valid_sources[0x1f]	14880	1			T2	2		T3	5		T13	11
valid_sources[0x20]	12680	1			T2	12		T3	5		T13	1
valid_sources[0x21]	15020	1			T2	6		T13	2		T14	5
valid_sources[0x22]	12860	1			T2	10		T3	9		T13	1
valid_sources[0x23]	14091	1			T2	12		T13	2		T14	7
valid_sources[0x24]	12341	1			T2	4		T3	6		T13	4
valid_sources[0x25]	14109	1			T2	1		T13	1		T14	1
valid_sources[0x26]	13248	1			T2	6		T3	21		T13	1
valid_sources[0x27]	12364	1			T2	1		T3	7		T13	3
valid_sources[0x28]	16248	1			T2	4		T3	4		T13	1
valid_sources[0x29]	15350	1			T2	5		T13	2		T14	3
valid_sources[0x2a]	14241	1			T2	6		T3	6		T13	2
valid_sources[0x2b]	12653	1			T2	17		T13	3		T15	20
valid_sources[0x2c]	16018	1			T2	3		T3	2		T13	3
valid_sources[0x2d]	12383	1			T2	4		T3	3		T13	2
valid_sources[0x2e]	12888	1			T2	3		T13	6		T15	2
valid_sources[0x2f]	14001	1			T2	7		T13	5		T15	8
valid_sources[0x30]	13530	1			T2	5		T3	7		T13	4
valid_sources[0x31]	13992	1			T13	5		T14	1		T15	3
valid_sources[0x32]	13700	1			T2	7		T3	4		T13	6
valid_sources[0x33]	12725	1			T2	3		T3	1		T13	5
valid_sources[0x34]	13700	1			T2	4		T13	4		T15	2
valid_sources[0x35]	14573	1			T3	3		T13	6		T14	7
valid_sources[0x36]	12094	1			T2	3		T14	1		T15	7
valid_sources[0x37]	12730	1			T2	15		T3	2		T13	3
valid_sources[0x38]	14350	1			T2	9		T13	6		T14	3
valid_sources[0x39]	13155	1			T2	14		T3	5		T13	5
valid_sources[0x3a]	14594	1			T2	8		T13	3		T14	4
valid_sources[0x3b]	43048	1			T2	7		T3	7		T13	6
valid_sources[0x3c]	15342	1			T2	1		T13	2		T14	3
valid_sources[0x3d]	13410	1			T2	5		T13	2		T16	1
valid_sources[0x3e]	18254	1			T2	2		T3	6		T13	5
valid_sources[0x3f]	13136	1			T2	10		T3	5		T13	1
valid_sources[0x40]	14375	1			T2	1		T13	1		T15	19
valid_sources[0x41]	13004	1			T2	3		T13	4		T14	6
valid_sources[0x42]	18216	1			T13	7		T14	7		T16	3
valid_sources[0x43]	13871	1			T2	10		T3	6		T13	4
valid_sources[0x44]	22921	1			T2	3		T13	4		T14	2
valid_sources[0x45]	12647	1			T1	276		T2	13		T13	3
valid_sources[0x46]	12340	1			T13	1		T14	2		T15	4
valid_sources[0x47]	12798	1			T2	2		T13	4		T14	2
valid_sources[0x48]	15192	1			T2	1		T13	2		T14	1
valid_sources[0x49]	18245	1			T3	4		T13	4		T15	1
valid_sources[0x4a]	13468	1			T2	8		T3	6		T13	2
valid_sources[0x4b]	13114	1			T2	3		T13	3		T14	1
valid_sources[0x4c]	13872	1			T2	12		T13	3		T18	3
valid_sources[0x4d]	12705	1			T2	16		T13	7		T15	5
valid_sources[0x4e]	13447	1			T3	2		T13	5		T15	3
valid_sources[0x4f]	13471	1			T2	3		T3	4		T13	3
valid_sources[0x50]	18579	1			T2	8		T3	6		T15	20
valid_sources[0x51]	13208	1			T2	2		T3	4		T13	4
valid_sources[0x52]	13110	1			T2	1		T3	23		T13	4
valid_sources[0x53]	14050	1			T2	4		T3	2		T13	4
valid_sources[0x54]	13006	1			T2	7		T13	1		T14	3
valid_sources[0x55]	12891	1			T13	1		T14	1		T15	7
valid_sources[0x56]	12424	1			T2	5		T13	1		T14	6
valid_sources[0x57]	13587	1			T2	3		T3	8		T13	2
valid_sources[0x58]	14255	1			T2	1		T3	4		T13	7
valid_sources[0x59]	15754	1			T2	3		T3	25		T13	2
valid_sources[0x5a]	15418	1			T2	2		T3	2		T13	1
valid_sources[0x5b]	13541	1			T2	15		T13	4		T14	4
valid_sources[0x5c]	13994	1			T3	4		T13	4		T14	1
valid_sources[0x5d]	12968	1			T2	4		T3	21		T13	8
valid_sources[0x5e]	13422	1			T2	5		T13	4		T14	1
valid_sources[0x5f]	22531	1			T2	1		T3	7		T13	2
valid_sources[0x60]	15099	1			T2	5		T3	19		T14	4
valid_sources[0x61]	12507	1			T2	6		T13	2		T18	1
valid_sources[0x62]	13758	1			T2	3		T3	2		T13	4
valid_sources[0x63]	13026	1			T3	3		T13	3		T14	3
valid_sources[0x64]	12434	1			T2	1		T3	5		T13	3
valid_sources[0x65]	12740	1			T2	4		T13	1		T15	9
valid_sources[0x66]	13422	1			T2	3		T3	9		T13	5
valid_sources[0x67]	12983	1			T2	2		T3	7		T13	4
valid_sources[0x68]	14452	1			T3	3		T13	1		T14	1
valid_sources[0x69]	13109	1			T2	3		T3	4		T14	3
valid_sources[0x6a]	12956	1			T2	3		T3	6		T13	5
valid_sources[0x6b]	14550	1			T2	3		T3	2		T13	1
valid_sources[0x6c]	12865	1			T2	10		T3	1		T13	7
valid_sources[0x6d]	14090	1			T2	1		T3	2		T13	3
valid_sources[0x6e]	12893	1			T2	1		T3	1		T14	1
valid_sources[0x6f]	13655	1			T2	2		T13	3		T15	4
valid_sources[0x70]	15085	1			T2	3		T13	1		T14	1
valid_sources[0x71]	12828	1			T2	5		T13	5		T14	1
valid_sources[0x72]	18705	1			T2	12		T3	6		T13	4
valid_sources[0x73]	12311	1			T2	3		T14	3		T15	9
valid_sources[0x74]	17277	1			T2	3		T3	5		T13	1
valid_sources[0x75]	12768	1			T2	11		T3	2		T13	3
valid_sources[0x76]	14748	1			T2	7		T13	5		T14	5
valid_sources[0x77]	13412	1			T2	1		T3	1		T13	5
valid_sources[0x78]	14136	1			T2	2		T14	4		T15	8
valid_sources[0x79]	24581	1			T2	3		T3	7		T13	1
valid_sources[0x7a]	14379	1			T2	4		T3	5		T13	4
valid_sources[0x7b]	13145	1			T2	3		T13	1		T15	8
valid_sources[0x7c]	28832	1			T2	7		T3	6		T13	2
valid_sources[0x7d]	15109	1			T2	12		T3	3		T13	3
valid_sources[0x7e]	12243	1			T2	3		T13	6		T16	3
valid_sources[0x7f]	13280	1			T2	8		T13	4		T14	6
valid_sources[0x80]	12746	1			T2	1		T14	6		T15	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

337394

1

T1

16

T2

187

T3

142

values[0x0]

all_enables

biggest_size

148831

1

T1

9

T2

104

T3

73

values[0x1]

all_enables

biggest_size

133134

1

T1

2

T2

81

T3

84