Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3369537	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

623782

1

T1

186

T2

129

T3

508

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3567748	1			T1	10426		T2	350		T3	596
values[0x0]	211719	1			T1	52		T2	41		T3	196
values[0x1]	213852	1			T1	57		T2	48		T3	196

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2305228	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1688091

1

T1

3596

T2

212

T3

607

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12315	1			T1	48		T2	1		T14	12
valid_sources[0x01]	12067	1			T1	43		T2	2		T14	10
valid_sources[0x02]	12911	1			T1	53		T2	2		T14	13
valid_sources[0x03]	16925	1			T1	41		T14	7		T15	15
valid_sources[0x04]	16887	1			T1	32		T2	3		T14	9
valid_sources[0x05]	11227	1			T1	46		T2	1		T14	11
valid_sources[0x06]	11437	1			T1	45		T2	3		T3	4
valid_sources[0x07]	13185	1			T1	46		T2	4		T14	15
valid_sources[0x08]	11677	1			T1	28		T2	2		T14	20
valid_sources[0x09]	12533	1			T1	44		T2	2		T14	14
valid_sources[0x0a]	13144	1			T1	42		T2	1		T14	10
valid_sources[0x0b]	12221	1			T1	41		T2	5		T3	19
valid_sources[0x0c]	33464	1			T1	39		T2	8		T14	9
valid_sources[0x0d]	12507	1			T1	42		T2	3		T14	8
valid_sources[0x0e]	14227	1			T1	34		T2	1		T3	26
valid_sources[0x0f]	11464	1			T1	26		T2	2		T14	17
valid_sources[0x10]	16205	1			T1	50		T2	2		T14	21
valid_sources[0x11]	12302	1			T1	42		T2	1		T14	11
valid_sources[0x12]	11759	1			T1	31		T2	2		T14	20
valid_sources[0x13]	11583	1			T1	36		T2	1		T14	8
valid_sources[0x14]	15548	1			T1	50		T2	3		T14	11
valid_sources[0x15]	11631	1			T1	48		T2	1		T3	44
valid_sources[0x16]	13950	1			T1	47		T2	1		T14	18
valid_sources[0x17]	17244	1			T1	46		T3	10		T14	13
valid_sources[0x18]	12734	1			T1	39		T2	1		T14	8
valid_sources[0x19]	11716	1			T1	41		T2	1		T14	13
valid_sources[0x1a]	13876	1			T1	37		T2	5		T3	15
valid_sources[0x1b]	11632	1			T1	36		T3	21		T14	18
valid_sources[0x1c]	12220	1			T1	40		T2	3		T14	12
valid_sources[0x1d]	12875	1			T1	37		T2	1		T14	8
valid_sources[0x1e]	11401	1			T1	45		T2	1		T14	9
valid_sources[0x1f]	13091	1			T1	58		T2	1		T3	8
valid_sources[0x20]	19838	1			T1	41		T2	3		T14	13
valid_sources[0x21]	17091	1			T1	47		T2	3		T14	13
valid_sources[0x22]	11860	1			T1	46		T2	1		T14	11
valid_sources[0x23]	13118	1			T1	43		T2	1		T14	3
valid_sources[0x24]	11910	1			T1	38		T2	1		T14	7
valid_sources[0x25]	12592	1			T1	45		T2	2		T14	6
valid_sources[0x26]	12148	1			T1	41		T2	1		T3	1
valid_sources[0x27]	11508	1			T1	33		T14	7		T15	1
valid_sources[0x28]	11441	1			T1	50		T2	3		T14	15
valid_sources[0x29]	12653	1			T1	35		T2	4		T14	6
valid_sources[0x2a]	13335	1			T1	35		T2	1		T14	13
valid_sources[0x2b]	11820	1			T1	51		T14	12		T15	13
valid_sources[0x2c]	13206	1			T1	43		T2	1		T14	6
valid_sources[0x2d]	11193	1			T1	37		T2	5		T3	12
valid_sources[0x2e]	12659	1			T1	39		T2	1		T14	14
valid_sources[0x2f]	12913	1			T1	30		T2	1		T14	15
valid_sources[0x30]	15079	1			T1	43		T2	3		T14	5
valid_sources[0x31]	12160	1			T1	50		T2	3		T3	30
valid_sources[0x32]	12246	1			T1	49		T2	7		T14	12
valid_sources[0x33]	12861	1			T1	31		T2	1		T14	16
valid_sources[0x34]	11379	1			T1	47		T2	3		T14	14
valid_sources[0x35]	12781	1			T1	41		T2	7		T14	16
valid_sources[0x36]	13542	1			T1	54		T2	1		T3	30
valid_sources[0x37]	12465	1			T1	40		T3	53		T14	14
valid_sources[0x38]	16706	1			T1	48		T2	4		T14	15
valid_sources[0x39]	16120	1			T1	27		T14	13		T15	5
valid_sources[0x3a]	18521	1			T1	45		T2	2		T14	8
valid_sources[0x3b]	11851	1			T1	41		T2	2		T14	10
valid_sources[0x3c]	12477	1			T1	42		T14	14		T15	20
valid_sources[0x3d]	17383	1			T1	43		T2	4		T14	5
valid_sources[0x3e]	11469	1			T1	36		T2	3		T14	13
valid_sources[0x3f]	15424	1			T1	34		T2	3		T3	20
valid_sources[0x40]	16952	1			T1	41		T14	13		T15	4
valid_sources[0x41]	13043	1			T1	47		T2	2		T3	9
valid_sources[0x42]	11520	1			T1	51		T14	16		T15	18
valid_sources[0x43]	13265	1			T1	53		T2	2		T14	3
valid_sources[0x44]	12171	1			T1	42		T2	1		T14	17
valid_sources[0x45]	11697	1			T1	37		T2	2		T14	4
valid_sources[0x46]	13486	1			T1	27		T2	4		T14	9
valid_sources[0x47]	12980	1			T1	33		T2	2		T14	15
valid_sources[0x48]	16060	1			T1	44		T2	4		T14	12
valid_sources[0x49]	12570	1			T1	41		T2	2		T14	6
valid_sources[0x4a]	11661	1			T1	38		T3	2		T14	18
valid_sources[0x4b]	11942	1			T1	46		T2	1		T14	7
valid_sources[0x4c]	11043	1			T1	50		T14	13		T15	17
valid_sources[0x4d]	13427	1			T1	37		T2	3		T14	12
valid_sources[0x4e]	11336	1			T1	28		T14	12		T15	3
valid_sources[0x4f]	12778	1			T1	36		T14	15		T15	6
valid_sources[0x50]	11488	1			T1	47		T14	13		T15	38
valid_sources[0x51]	17033	1			T1	37		T2	2		T14	15
valid_sources[0x52]	11460	1			T1	53		T2	2		T14	8
valid_sources[0x53]	11767	1			T1	40		T2	1		T3	18
valid_sources[0x54]	12023	1			T1	44		T2	2		T14	18
valid_sources[0x55]	11864	1			T1	34		T14	12		T15	1
valid_sources[0x56]	11464	1			T1	41		T14	21		T15	27
valid_sources[0x57]	11760	1			T1	43		T2	4		T14	5
valid_sources[0x58]	11941	1			T1	36		T2	4		T14	16
valid_sources[0x59]	11887	1			T1	44		T2	2		T14	11
valid_sources[0x5a]	64275	1			T1	30		T2	1		T14	15
valid_sources[0x5b]	11750	1			T1	56		T2	1		T14	11
valid_sources[0x5c]	14072	1			T1	37		T2	5		T3	8
valid_sources[0x5d]	11688	1			T1	38		T14	3		T15	1
valid_sources[0x5e]	12441	1			T1	45		T2	2		T3	14
valid_sources[0x5f]	11129	1			T1	33		T2	1		T14	9
valid_sources[0x60]	11661	1			T1	56		T14	9		T15	17
valid_sources[0x61]	11375	1			T1	38		T2	1		T14	9
valid_sources[0x62]	12175	1			T1	28		T2	2		T14	13
valid_sources[0x63]	12678	1			T1	42		T3	21		T14	15
valid_sources[0x64]	12161	1			T1	36		T2	1		T14	9
valid_sources[0x65]	20063	1			T1	34		T2	1		T14	19
valid_sources[0x66]	12041	1			T1	42		T3	6		T14	14
valid_sources[0x67]	12854	1			T1	39		T2	5		T3	65
valid_sources[0x68]	11169	1			T1	32		T2	1		T3	12
valid_sources[0x69]	11432	1			T1	44		T2	1		T14	8
valid_sources[0x6a]	21033	1			T1	50		T2	2		T14	10
valid_sources[0x6b]	17067	1			T1	35		T2	1		T14	5
valid_sources[0x6c]	39122	1			T1	33		T2	4		T14	8
valid_sources[0x6d]	12245	1			T1	37		T2	1		T14	12
valid_sources[0x6e]	12004	1			T1	44		T2	3		T14	10
valid_sources[0x6f]	11597	1			T1	49		T14	8		T15	23
valid_sources[0x70]	12398	1			T1	38		T14	9		T15	1
valid_sources[0x71]	11413	1			T1	55		T14	11		T15	15
valid_sources[0x72]	12518	1			T1	41		T2	2		T14	19
valid_sources[0x73]	11286	1			T1	40		T2	1		T14	6
valid_sources[0x74]	13074	1			T1	43		T2	2		T14	12
valid_sources[0x75]	12918	1			T1	34		T2	2		T14	13
valid_sources[0x76]	11408	1			T1	45		T2	2		T14	14
valid_sources[0x77]	12929	1			T1	52		T2	4		T14	21
valid_sources[0x78]	18291	1			T1	48		T2	3		T14	13
valid_sources[0x79]	15340	1			T1	46		T2	1		T14	7
valid_sources[0x7a]	12949	1			T1	35		T2	2		T14	21
valid_sources[0x7b]	12060	1			T1	34		T2	4		T3	2
valid_sources[0x7c]	15741	1			T1	35		T14	6		T15	5
valid_sources[0x7d]	12373	1			T1	48		T2	1		T14	6
valid_sources[0x7e]	11702	1			T1	40		T14	6		T15	27
valid_sources[0x7f]	18448	1			T1	37		T2	2		T14	6
valid_sources[0x80]	20756	1			T1	43		T2	2		T3	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

335529

1

T1

156

T2

102

T3

232

values[0x0]

all_enables

biggest_size

152081

1

T1

21

T2

19

T3

140

values[0x1]

all_enables

biggest_size

136172

1

T1

9

T2

8

T3

136