Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	25563227	16526	0	0
attest_sw_binding_0_rd_A	25563227	2840	0	0
attest_sw_binding_1_rd_A	25563227	2814	0	0
attest_sw_binding_2_rd_A	25563227	2795	0	0
attest_sw_binding_3_rd_A	25563227	2828	0	0
attest_sw_binding_4_rd_A	25563227	2660	0	0
attest_sw_binding_5_rd_A	25563227	2802	0	0
attest_sw_binding_6_rd_A	25563227	2997	0	0
attest_sw_binding_7_rd_A	25563227	2955	0	0
intr_enable_rd_A	25563227	3590	0	0
key_version_rd_A	25563227	2854	0	0
max_creator_key_ver_regwen_rd_A	25563227	2861	0	0
max_owner_int_key_ver_regwen_rd_A	25563227	2724	0	0
max_owner_key_ver_regwen_rd_A	25563227	2846	0	0
reseed_interval_regwen_rd_A	25563227	2695	0	0
salt_0_rd_A	25563227	2962	0	0
salt_1_rd_A	25563227	2933	0	0
salt_2_rd_A	25563227	2950	0	0
salt_3_rd_A	25563227	2819	0	0
salt_4_rd_A	25563227	2738	0	0
salt_5_rd_A	25563227	2749	0	0
salt_6_rd_A	25563227	2628	0	0
salt_7_rd_A	25563227	2818	0	0
sealing_sw_binding_0_rd_A	25563227	2892	0	0
sealing_sw_binding_1_rd_A	25563227	2801	0	0
sealing_sw_binding_2_rd_A	25563227	2742	0	0
sealing_sw_binding_3_rd_A	25563227	2739	0	0
sealing_sw_binding_4_rd_A	25563227	2615	0	0
sealing_sw_binding_5_rd_A	25563227	2846	0	0
sealing_sw_binding_6_rd_A	25563227	2846	0	0
sealing_sw_binding_7_rd_A	25563227	2752	0	0
sideload_clear_rd_A	25563227	2616	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25563227	16526	0	0
T5	169386	0	0	0
T18	19629	0	0	0
T42	15143	389	0	0
T45	16818	0	0	0
T49	16909	0	0	0
T66	0	153	0	0
T70	0	836	0	0
T79	0	301	0	0
T97	8650	0	0	0
T99	1004	0	0	0
T100	0	607	0	0
T110	0	356	0	0
T127	0	783	0	0
T128	0	56	0	0
T133	0	791	0	0
T134	0	46	0	0
T135	15580	0	0	0
T136	201498	0	0	0
T137	10084	0	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25563227	2840	0	0
T48	0	30	0	0
T88	2589	0	0	0
T96	8468	0	0	0
T111	0	46	0	0
T128	54180	22	0	0
T129	2948	0	0	0
T134	0	12	0	0
T183	0	42	0	0
T184	0	26	0	0
T185	0	47	0	0
T186	0	54	0	0
T187	0	20	0	0
T188	0	57	0	0
T189	6522	0	0	0
T190	3330	0	0	0
T191	3012	0	0	0
T192	3982	0	0	0
T193	7039	0	0	0
T194	139690	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25563227	2814	0	0
T48	0	45	0	0
T88	2589	0	0	0
T96	8468	0	0	0
T111	0	67	0	0
T128	54180	21	0	0
T129	2948	0	0	0
T134	0	18	0	0
T183	0	20	0	0
T184	0	38	0	0
T185	0	47	0	0
T186	0	46	0	0
T187	0	14	0	0
T188	0	44	0	0
T189	6522	0	0	0
T190	3330	0	0	0
T191	3012	0	0	0
T192	3982	0	0	0
T193	7039	0	0	0
T194	139690	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25563227	2795	0	0
T48	0	28	0	0
T88	2589	0	0	0
T96	8468	0	0	0
T111	0	64	0	0
T128	54180	32	0	0
T129	2948	0	0	0
T134	0	12	0	0
T183	0	44	0	0
T184	0	34	0	0
T185	0	47	0	0
T186	0	52	0	0
T187	0	26	0	0
T188	0	67	0	0
T189	6522	0	0	0
T190	3330	0	0	0
T191	3012	0	0	0
T192	3982	0	0	0
T193	7039	0	0	0
T194	139690	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25563227	2828	0	0
T48	0	35	0	0
T88	2589	0	0	0
T96	8468	0	0	0
T111	0	67	0	0
T128	54180	46	0	0
T129	2948	0	0	0
T134	0	38	0	0
T183	0	31	0	0
T184	0	14	0	0
T185	0	50	0	0
T186	0	55	0	0
T187	0	18	0	0
T188	0	34	0	0
T189	6522	0	0	0
T190	3330	0	0	0
T191	3012	0	0	0
T192	3982	0	0	0
T193	7039	0	0	0
T194	139690	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25563227	2660	0	0
T48	0	27	0	0
T88	2589	0	0	0
T96	8468	0	0	0
T111	0	55	0	0
T128	54180	27	0	0
T129	2948	0	0	0
T134	0	32	0	0
T183	0	31	0	0
T184	0	25	0	0
T185	0	40	0	0
T186	0	41	0	0
T187	0	19	0	0
T188	0	61	0	0
T189	6522	0	0	0
T190	3330	0	0	0
T191	3012	0	0	0
T192	3982	0	0	0
T193	7039	0	0	0
T194	139690	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25563227	2802	0	0
T48	0	24	0	0
T88	2589	0	0	0
T96	8468	0	0	0
T111	0	37	0	0
T128	54180	36	0	0
T129	2948	0	0	0
T134	0	29	0	0
T183	0	16	0	0
T184	0	30	0	0
T185	0	57	0	0
T186	0	66	0	0
T187	0	22	0	0
T188	0	43	0	0
T189	6522	0	0	0
T190	3330	0	0	0
T191	3012	0	0	0
T192	3982	0	0	0
T193	7039	0	0	0
T194	139690	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25563227	2997	0	0
T48	0	15	0	0
T88	2589	0	0	0
T96	8468	0	0	0
T111	0	39	0	0
T128	54180	32	0	0
T129	2948	0	0	0
T134	0	10	0	0
T183	0	35	0	0
T184	0	18	0	0
T185	0	72	0	0
T186	0	45	0	0
T187	0	17	0	0
T188	0	58	0	0
T189	6522	0	0	0
T190	3330	0	0	0
T191	3012	0	0	0
T192	3982	0	0	0
T193	7039	0	0	0
T194	139690	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25563227	2955	0	0
T48	0	43	0	0
T88	2589	0	0	0
T96	8468	0	0	0
T111	0	35	0	0
T128	54180	23	0	0
T129	2948	0	0	0
T134	0	34	0	0
T183	0	22	0	0
T184	0	44	0	0
T185	0	72	0	0
T186	0	92	0	0
T187	0	13	0	0
T188	0	32	0	0
T189	6522	0	0	0
T190	3330	0	0	0
T191	3012	0	0	0
T192	3982	0	0	0
T193	7039	0	0	0
T194	139690	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25563227	3590	0	0
T16	139245	35	0	0
T17	121199	0	0	0
T33	12961	0	0	0
T43	0	45	0	0
T44	0	11	0	0
T55	0	11	0	0
T56	0	92	0	0
T71	0	39	0	0
T72	0	19	0	0
T85	5567	0	0	0
T116	3600	0	0	0
T117	4548	0	0	0
T128	0	19	0	0
T134	0	31	0	0
T138	15107	0	0	0
T139	4783	0	0	0
T140	7452	0	0	0
T141	133421	0	0	0
T195	0	29	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25563227	2854	0	0
T48	0	40	0	0
T88	2589	0	0	0
T96	8468	0	0	0
T111	0	53	0	0
T128	54180	32	0	0
T129	2948	0	0	0
T134	0	31	0	0
T183	0	8	0	0
T184	0	22	0	0
T185	0	85	0	0
T186	0	51	0	0
T187	0	29	0	0
T188	0	54	0	0
T189	6522	0	0	0
T190	3330	0	0	0
T191	3012	0	0	0
T192	3982	0	0	0
T193	7039	0	0	0
T194	139690	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25563227	2861	0	0
T48	0	65	0	0
T88	2589	0	0	0
T96	8468	0	0	0
T111	0	58	0	0
T128	54180	43	0	0
T129	2948	0	0	0
T134	0	8	0	0
T183	0	32	0	0
T184	0	33	0	0
T185	0	63	0	0
T186	0	61	0	0
T187	0	34	0	0
T188	0	70	0	0
T189	6522	0	0	0
T190	3330	0	0	0
T191	3012	0	0	0
T192	3982	0	0	0
T193	7039	0	0	0
T194	139690	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25563227	2724	0	0
T48	0	37	0	0
T88	2589	0	0	0
T96	8468	0	0	0
T111	0	39	0	0
T128	54180	37	0	0
T129	2948	0	0	0
T134	0	7	0	0
T183	0	29	0	0
T184	0	29	0	0
T185	0	47	0	0
T186	0	38	0	0
T187	0	19	0	0
T188	0	26	0	0
T189	6522	0	0	0
T190	3330	0	0	0
T191	3012	0	0	0
T192	3982	0	0	0
T193	7039	0	0	0
T194	139690	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25563227	2846	0	0
T48	0	31	0	0
T88	2589	0	0	0
T96	8468	0	0	0
T111	0	73	0	0
T128	54180	27	0	0
T129	2948	0	0	0
T134	0	10	0	0
T183	0	30	0	0
T184	0	20	0	0
T185	0	56	0	0
T186	0	42	0	0
T187	0	36	0	0
T188	0	64	0	0
T189	6522	0	0	0
T190	3330	0	0	0
T191	3012	0	0	0
T192	3982	0	0	0
T193	7039	0	0	0
T194	139690	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25563227	2695	0	0
T48	0	31	0	0
T88	2589	0	0	0
T96	8468	0	0	0
T111	0	23	0	0
T128	54180	27	0	0
T129	2948	0	0	0
T134	0	9	0	0
T183	0	29	0	0
T184	0	13	0	0
T185	0	82	0	0
T186	0	49	0	0
T187	0	10	0	0
T188	0	66	0	0
T189	6522	0	0	0
T190	3330	0	0	0
T191	3012	0	0	0
T192	3982	0	0	0
T193	7039	0	0	0
T194	139690	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25563227	2962	0	0
T48	0	14	0	0
T88	2589	0	0	0
T96	8468	0	0	0
T111	0	88	0	0
T128	54180	29	0	0
T129	2948	0	0	0
T134	0	31	0	0
T183	0	37	0	0
T184	0	30	0	0
T185	0	67	0	0
T186	0	40	0	0
T187	0	17	0	0
T188	0	58	0	0
T189	6522	0	0	0
T190	3330	0	0	0
T191	3012	0	0	0
T192	3982	0	0	0
T193	7039	0	0	0
T194	139690	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25563227	2933	0	0
T48	0	25	0	0
T88	2589	0	0	0
T96	8468	0	0	0
T111	0	54	0	0
T128	54180	52	0	0
T129	2948	0	0	0
T134	0	16	0	0
T183	0	27	0	0
T184	0	31	0	0
T185	0	68	0	0
T186	0	50	0	0
T187	0	15	0	0
T188	0	83	0	0
T189	6522	0	0	0
T190	3330	0	0	0
T191	3012	0	0	0
T192	3982	0	0	0
T193	7039	0	0	0
T194	139690	0	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25563227	2950	0	0
T48	0	37	0	0
T88	2589	0	0	0
T96	8468	0	0	0
T111	0	38	0	0
T128	54180	29	0	0
T129	2948	0	0	0
T134	0	8	0	0
T183	0	22	0	0
T184	0	21	0	0
T185	0	61	0	0
T186	0	66	0	0
T187	0	18	0	0
T188	0	70	0	0
T189	6522	0	0	0
T190	3330	0	0	0
T191	3012	0	0	0
T192	3982	0	0	0
T193	7039	0	0	0
T194	139690	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25563227	2819	0	0
T48	0	33	0	0
T88	2589	0	0	0
T96	8468	0	0	0
T111	0	37	0	0
T128	54180	46	0	0
T129	2948	0	0	0
T134	0	10	0	0
T183	0	42	0	0
T184	0	38	0	0
T185	0	57	0	0
T186	0	41	0	0
T187	0	16	0	0
T188	0	64	0	0
T189	6522	0	0	0
T190	3330	0	0	0
T191	3012	0	0	0
T192	3982	0	0	0
T193	7039	0	0	0
T194	139690	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25563227	2738	0	0
T48	0	26	0	0
T88	2589	0	0	0
T96	8468	0	0	0
T111	0	21	0	0
T128	54180	34	0	0
T129	2948	0	0	0
T145	0	30	0	0
T183	0	20	0	0
T184	0	36	0	0
T185	0	48	0	0
T186	0	42	0	0
T187	0	12	0	0
T188	0	38	0	0
T189	6522	0	0	0
T190	3330	0	0	0
T191	3012	0	0	0
T192	3982	0	0	0
T193	7039	0	0	0
T194	139690	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25563227	2749	0	0
T48	0	58	0	0
T88	2589	0	0	0
T96	8468	0	0	0
T111	0	63	0	0
T128	54180	34	0	0
T129	2948	0	0	0
T134	0	11	0	0
T183	0	18	0	0
T184	0	29	0	0
T185	0	44	0	0
T186	0	39	0	0
T187	0	15	0	0
T188	0	59	0	0
T189	6522	0	0	0
T190	3330	0	0	0
T191	3012	0	0	0
T192	3982	0	0	0
T193	7039	0	0	0
T194	139690	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25563227	2628	0	0
T48	0	27	0	0
T88	2589	0	0	0
T96	8468	0	0	0
T111	0	66	0	0
T128	54180	23	0	0
T129	2948	0	0	0
T134	0	26	0	0
T183	0	35	0	0
T184	0	13	0	0
T185	0	26	0	0
T186	0	48	0	0
T187	0	5	0	0
T188	0	38	0	0
T189	6522	0	0	0
T190	3330	0	0	0
T191	3012	0	0	0
T192	3982	0	0	0
T193	7039	0	0	0
T194	139690	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25563227	2818	0	0
T48	0	24	0	0
T88	2589	0	0	0
T96	8468	0	0	0
T111	0	35	0	0
T128	54180	31	0	0
T129	2948	0	0	0
T134	0	20	0	0
T183	0	21	0	0
T184	0	51	0	0
T185	0	91	0	0
T186	0	70	0	0
T187	0	8	0	0
T188	0	48	0	0
T189	6522	0	0	0
T190	3330	0	0	0
T191	3012	0	0	0
T192	3982	0	0	0
T193	7039	0	0	0
T194	139690	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25563227	2892	0	0
T48	0	47	0	0
T88	2589	0	0	0
T96	8468	0	0	0
T128	54180	46	0	0
T129	2948	0	0	0
T134	0	15	0	0
T183	0	21	0	0
T184	0	25	0	0
T185	0	52	0	0
T186	0	52	0	0
T187	0	21	0	0
T188	0	83	0	0
T189	6522	0	0	0
T190	3330	0	0	0
T191	3012	0	0	0
T192	3982	0	0	0
T193	7039	0	0	0
T194	139690	0	0	0
T196	0	2	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25563227	2801	0	0
T48	0	27	0	0
T88	2589	0	0	0
T96	8468	0	0	0
T111	0	75	0	0
T128	54180	44	0	0
T129	2948	0	0	0
T134	0	42	0	0
T183	0	28	0	0
T184	0	27	0	0
T185	0	46	0	0
T186	0	36	0	0
T187	0	31	0	0
T188	0	43	0	0
T189	6522	0	0	0
T190	3330	0	0	0
T191	3012	0	0	0
T192	3982	0	0	0
T193	7039	0	0	0
T194	139690	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25563227	2742	0	0
T48	0	29	0	0
T88	2589	0	0	0
T96	8468	0	0	0
T111	0	43	0	0
T128	54180	35	0	0
T129	2948	0	0	0
T134	0	13	0	0
T183	0	32	0	0
T184	0	29	0	0
T185	0	41	0	0
T186	0	74	0	0
T187	0	11	0	0
T188	0	56	0	0
T189	6522	0	0	0
T190	3330	0	0	0
T191	3012	0	0	0
T192	3982	0	0	0
T193	7039	0	0	0
T194	139690	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25563227	2739	0	0
T48	0	24	0	0
T88	2589	0	0	0
T96	8468	0	0	0
T111	0	47	0	0
T128	54180	38	0	0
T129	2948	0	0	0
T134	0	3	0	0
T183	0	17	0	0
T184	0	25	0	0
T185	0	70	0	0
T186	0	38	0	0
T187	0	24	0	0
T188	0	63	0	0
T189	6522	0	0	0
T190	3330	0	0	0
T191	3012	0	0	0
T192	3982	0	0	0
T193	7039	0	0	0
T194	139690	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25563227	2615	0	0
T48	0	43	0	0
T88	2589	0	0	0
T96	8468	0	0	0
T111	0	32	0	0
T128	54180	13	0	0
T129	2948	0	0	0
T134	0	15	0	0
T183	0	18	0	0
T184	0	14	0	0
T185	0	59	0	0
T186	0	69	0	0
T187	0	12	0	0
T188	0	60	0	0
T189	6522	0	0	0
T190	3330	0	0	0
T191	3012	0	0	0
T192	3982	0	0	0
T193	7039	0	0	0
T194	139690	0	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25563227	2846	0	0
T48	0	30	0	0
T88	2589	0	0	0
T96	8468	0	0	0
T128	54180	32	0	0
T129	2948	0	0	0
T134	0	8	0	0
T183	0	36	0	0
T184	0	38	0	0
T185	0	72	0	0
T186	0	48	0	0
T187	0	4	0	0
T188	0	50	0	0
T189	6522	0	0	0
T190	3330	0	0	0
T191	3012	0	0	0
T192	3982	0	0	0
T193	7039	0	0	0
T194	139690	0	0	0
T197	0	6	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25563227	2846	0	0
T48	0	16	0	0
T88	2589	0	0	0
T96	8468	0	0	0
T128	54180	29	0	0
T129	2948	0	0	0
T134	0	3	0	0
T183	0	24	0	0
T184	0	43	0	0
T185	0	55	0	0
T186	0	54	0	0
T187	0	26	0	0
T188	0	57	0	0
T189	6522	0	0	0
T190	3330	0	0	0
T191	3012	0	0	0
T192	3982	0	0	0
T193	7039	0	0	0
T194	139690	0	0	0
T198	0	3	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25563227	2752	0	0
T48	0	25	0	0
T88	2589	0	0	0
T96	8468	0	0	0
T111	0	27	0	0
T128	54180	18	0	0
T129	2948	0	0	0
T134	0	30	0	0
T183	0	56	0	0
T184	0	49	0	0
T185	0	51	0	0
T186	0	45	0	0
T187	0	6	0	0
T188	0	90	0	0
T189	6522	0	0	0
T190	3330	0	0	0
T191	3012	0	0	0
T192	3982	0	0	0
T193	7039	0	0	0
T194	139690	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25563227	2616	0	0
T48	0	18	0	0
T88	2589	0	0	0
T96	8468	0	0	0
T111	0	62	0	0
T128	54180	23	0	0
T129	2948	0	0	0
T134	0	24	0	0
T183	0	9	0	0
T184	0	28	0	0
T185	0	75	0	0
T186	0	56	0	0
T187	0	15	0	0
T188	0	31	0	0
T189	6522	0	0	0
T190	3330	0	0	0
T191	3012	0	0	0
T192	3982	0	0	0
T193	7039	0	0	0
T194	139690	0	0	0