Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3144228	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

603172

1

T1

132

T2

368

T3

404

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3336560	1			T1	295		T2	2249		T3	734
values[0x0]	203731	1			T1	55		T2	199		T3	98
values[0x1]	207109	1			T1	62		T2	147		T3	116

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2152317	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1595083

1

T1

178

T2

1017

T3

525

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12004	1			T1	3		T2	18		T3	7
valid_sources[0x01]	16659	1			T2	10		T3	4		T11	7
valid_sources[0x02]	12245	1			T1	2		T2	14		T3	4
valid_sources[0x03]	13401	1			T1	2		T2	20		T3	4
valid_sources[0x04]	14227	1			T1	1		T2	17		T11	5
valid_sources[0x05]	19930	1			T1	1		T2	4		T3	2
valid_sources[0x06]	11970	1			T1	4		T2	9		T3	5
valid_sources[0x07]	13381	1			T2	7		T11	9		T12	4
valid_sources[0x08]	13964	1			T1	1		T2	12		T3	4
valid_sources[0x09]	12259	1			T1	2		T2	2		T3	3
valid_sources[0x0a]	11556	1			T1	1		T2	5		T3	3
valid_sources[0x0b]	12411	1			T1	3		T2	15		T3	3
valid_sources[0x0c]	19668	1			T1	1		T2	13		T3	7
valid_sources[0x0d]	15492	1			T2	17		T3	3		T11	7
valid_sources[0x0e]	13273	1			T1	1		T2	7		T3	2
valid_sources[0x0f]	14734	1			T1	2		T2	9		T3	7
valid_sources[0x10]	11903	1			T1	1		T2	17		T3	4
valid_sources[0x11]	20646	1			T2	3		T3	2		T11	4
valid_sources[0x12]	12409	1			T1	1		T2	13		T3	1
valid_sources[0x13]	13579	1			T1	1		T2	4		T3	3
valid_sources[0x14]	14712	1			T1	2		T2	13		T3	13
valid_sources[0x15]	12848	1			T2	12		T3	4		T11	6
valid_sources[0x16]	13132	1			T1	2		T2	3		T3	7
valid_sources[0x17]	12515	1			T1	1		T2	8		T3	2
valid_sources[0x18]	11633	1			T1	1		T2	10		T3	3
valid_sources[0x19]	12110	1			T1	2		T2	9		T3	3
valid_sources[0x1a]	12188	1			T1	1		T2	10		T3	9
valid_sources[0x1b]	15094	1			T1	2		T2	13		T3	5
valid_sources[0x1c]	13178	1			T1	3		T2	9		T3	1
valid_sources[0x1d]	16070	1			T1	2		T2	13		T3	4
valid_sources[0x1e]	13427	1			T1	3		T2	8		T3	6
valid_sources[0x1f]	13566	1			T2	6		T3	9		T11	7
valid_sources[0x20]	14413	1			T1	3		T2	15		T3	1
valid_sources[0x21]	12493	1			T1	1		T2	22		T3	1
valid_sources[0x22]	20637	1			T1	2		T2	17		T3	2
valid_sources[0x23]	12806	1			T1	1		T2	11		T3	3
valid_sources[0x24]	12216	1			T2	7		T3	4		T11	7
valid_sources[0x25]	12134	1			T1	1		T2	15		T3	3
valid_sources[0x26]	18764	1			T2	3		T3	1		T11	6
valid_sources[0x27]	11989	1			T1	4		T2	13		T3	2
valid_sources[0x28]	11878	1			T1	2		T2	4		T3	3
valid_sources[0x29]	12249	1			T1	1		T2	9		T3	5
valid_sources[0x2a]	15836	1			T1	1		T2	7		T3	1
valid_sources[0x2b]	13797	1			T1	1		T2	11		T3	3
valid_sources[0x2c]	11460	1			T1	2		T2	11		T3	11
valid_sources[0x2d]	20012	1			T2	18		T3	2		T11	11
valid_sources[0x2e]	21454	1			T2	18		T3	2		T11	2
valid_sources[0x2f]	13085	1			T1	3		T2	10		T3	1
valid_sources[0x30]	13751	1			T1	2		T2	12		T3	7
valid_sources[0x31]	12592	1			T1	4		T2	15		T3	8
valid_sources[0x32]	12826	1			T1	1		T2	5		T3	5
valid_sources[0x33]	14405	1			T1	1		T2	22		T3	6
valid_sources[0x34]	12459	1			T1	1		T2	18		T3	2
valid_sources[0x35]	12311	1			T1	2		T2	8		T3	2
valid_sources[0x36]	14176	1			T1	1		T2	17		T3	1
valid_sources[0x37]	12826	1			T1	2		T2	7		T3	3
valid_sources[0x38]	13843	1			T1	1		T2	8		T3	6
valid_sources[0x39]	12915	1			T1	3		T2	10		T3	2
valid_sources[0x3a]	12753	1			T2	19		T3	1		T11	4
valid_sources[0x3b]	13202	1			T1	1		T2	4		T3	1
valid_sources[0x3c]	14243	1			T1	1		T2	9		T3	4
valid_sources[0x3d]	12153	1			T2	15		T3	2		T11	8
valid_sources[0x3e]	11760	1			T1	1		T2	12		T3	9
valid_sources[0x3f]	16088	1			T1	1		T2	6		T3	5
valid_sources[0x40]	16623	1			T1	2		T2	12		T3	7
valid_sources[0x41]	13196	1			T2	5		T3	3		T14	4
valid_sources[0x42]	11843	1			T1	1		T2	12		T3	11
valid_sources[0x43]	12706	1			T2	6		T3	6		T11	3
valid_sources[0x44]	11776	1			T1	1		T2	16		T3	5
valid_sources[0x45]	13438	1			T1	2		T2	7		T3	4
valid_sources[0x46]	14151	1			T1	1		T2	5		T3	2
valid_sources[0x47]	13671	1			T1	5		T2	13		T3	3
valid_sources[0x48]	15258	1			T1	3		T2	8		T3	1
valid_sources[0x49]	24254	1			T1	1		T2	10		T3	3
valid_sources[0x4a]	17352	1			T1	3		T2	7		T3	4
valid_sources[0x4b]	14009	1			T2	6		T3	1		T11	7
valid_sources[0x4c]	21770	1			T1	3		T2	13		T3	11
valid_sources[0x4d]	19165	1			T1	1		T2	24		T3	2
valid_sources[0x4e]	18549	1			T1	2		T2	7		T3	3
valid_sources[0x4f]	12823	1			T1	1		T2	10		T3	3
valid_sources[0x50]	12345	1			T1	3		T2	8		T3	2
valid_sources[0x51]	11906	1			T1	2		T2	7		T3	6
valid_sources[0x52]	14061	1			T1	2		T2	25		T3	6
valid_sources[0x53]	13148	1			T1	1		T2	8		T3	1
valid_sources[0x54]	13781	1			T1	1		T2	2		T3	2
valid_sources[0x55]	14694	1			T1	2		T2	2		T3	4
valid_sources[0x56]	13101	1			T1	3		T2	3		T3	7
valid_sources[0x57]	50241	1			T1	1		T2	8		T3	6
valid_sources[0x58]	11977	1			T1	1		T2	8		T3	4
valid_sources[0x59]	13500	1			T2	6		T3	3		T11	3
valid_sources[0x5a]	13027	1			T1	2		T2	4		T3	5
valid_sources[0x5b]	15414	1			T1	3		T2	10		T3	4
valid_sources[0x5c]	13363	1			T1	4		T2	14		T3	4
valid_sources[0x5d]	16258	1			T1	1		T2	12		T3	2
valid_sources[0x5e]	13123	1			T1	1		T2	15		T11	6
valid_sources[0x5f]	14847	1			T2	6		T3	9		T11	5
valid_sources[0x60]	16584	1			T1	2		T2	21		T3	2
valid_sources[0x61]	13056	1			T1	3		T2	7		T3	5
valid_sources[0x62]	20993	1			T1	4		T2	15		T3	7
valid_sources[0x63]	13913	1			T1	5		T2	16		T3	5
valid_sources[0x64]	12989	1			T1	1		T2	15		T3	7
valid_sources[0x65]	15888	1			T1	3		T2	9		T3	3
valid_sources[0x66]	11283	1			T1	3		T2	8		T3	2
valid_sources[0x67]	11689	1			T1	1		T2	12		T3	3
valid_sources[0x68]	12524	1			T1	1		T2	7		T11	8
valid_sources[0x69]	12024	1			T2	10		T11	7		T15	2
valid_sources[0x6a]	12072	1			T2	5		T3	4		T11	3
valid_sources[0x6b]	13591	1			T2	2		T3	2		T11	6
valid_sources[0x6c]	12160	1			T1	3		T2	2		T3	1
valid_sources[0x6d]	12725	1			T1	3		T2	15		T3	2
valid_sources[0x6e]	19176	1			T1	1		T2	13		T3	6
valid_sources[0x6f]	13574	1			T1	1		T2	16		T3	4
valid_sources[0x70]	12227	1			T1	2		T2	8		T3	1
valid_sources[0x71]	13650	1			T1	1		T2	17		T3	1
valid_sources[0x72]	12082	1			T1	4		T2	7		T3	6
valid_sources[0x73]	12443	1			T1	3		T2	19		T3	2
valid_sources[0x74]	13670	1			T1	1		T2	7		T3	1
valid_sources[0x75]	12749	1			T1	1		T2	18		T3	2
valid_sources[0x76]	13096	1			T1	1		T2	5		T3	2
valid_sources[0x77]	13545	1			T1	1		T2	16		T3	5
valid_sources[0x78]	14185	1			T1	3		T2	18		T3	4
valid_sources[0x79]	12639	1			T1	1		T2	8		T3	1
valid_sources[0x7a]	15161	1			T1	1		T2	9		T3	11
valid_sources[0x7b]	12080	1			T1	2		T2	15		T3	1
valid_sources[0x7c]	12278	1			T1	1		T2	15		T11	10
valid_sources[0x7d]	13113	1			T1	2		T2	3		T3	2
valid_sources[0x7e]	12042	1			T1	3		T2	7		T11	2
valid_sources[0x7f]	12329	1			T1	1		T2	6		T3	6
valid_sources[0x80]	12332	1			T2	4		T3	5		T11	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

321575

1

T1

95

T2

112

T3

331

values[0x0]

all_enables

biggest_size

147768

1

T1

25

T2

157

T3

44

values[0x1]

all_enables

biggest_size

133829

1

T1

12

T2

99

T3

29