Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	22843288	16124	0	0
attest_sw_binding_0_rd_A	22843288	2732	0	0
attest_sw_binding_1_rd_A	22843288	2842	0	0
attest_sw_binding_2_rd_A	22843288	2818	0	0
attest_sw_binding_3_rd_A	22843288	2680	0	0
attest_sw_binding_4_rd_A	22843288	2792	0	0
attest_sw_binding_5_rd_A	22843288	2611	0	0
attest_sw_binding_6_rd_A	22843288	2896	0	0
attest_sw_binding_7_rd_A	22843288	2770	0	0
intr_enable_rd_A	22843288	3203	0	0
key_version_rd_A	22843288	2831	0	0
max_creator_key_ver_regwen_rd_A	22843288	2669	0	0
max_owner_int_key_ver_regwen_rd_A	22843288	2703	0	0
max_owner_key_ver_regwen_rd_A	22843288	2706	0	0
reseed_interval_regwen_rd_A	22843288	2637	0	0
salt_0_rd_A	22843288	2793	0	0
salt_1_rd_A	22843288	2757	0	0
salt_2_rd_A	22843288	2710	0	0
salt_3_rd_A	22843288	2743	0	0
salt_4_rd_A	22843288	2782	0	0
salt_5_rd_A	22843288	2773	0	0
salt_6_rd_A	22843288	2665	0	0
salt_7_rd_A	22843288	2777	0	0
sealing_sw_binding_0_rd_A	22843288	2719	0	0
sealing_sw_binding_1_rd_A	22843288	2711	0	0
sealing_sw_binding_2_rd_A	22843288	2600	0	0
sealing_sw_binding_3_rd_A	22843288	2879	0	0
sealing_sw_binding_4_rd_A	22843288	2756	0	0
sealing_sw_binding_5_rd_A	22843288	2716	0	0
sealing_sw_binding_6_rd_A	22843288	2773	0	0
sealing_sw_binding_7_rd_A	22843288	2703	0	0
sideload_clear_rd_A	22843288	2736	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22843288	16124	0	0
T5	0	388	0	0
T55	24829	474	0	0
T67	3010	0	0	0
T106	29894	906	0	0
T109	0	82	0	0
T120	0	54	0	0
T121	0	178	0	0
T123	0	76	0	0
T124	0	89	0	0
T125	0	349	0	0
T126	26470	0	0	0
T127	1268	0	0	0
T128	3484	0	0	0
T129	4408	0	0	0
T130	6671	0	0	0
T131	2519	0	0	0
T132	3782	0	0	0
T163	0	1094	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22843288	2732	0	0
T42	4388	0	0	0
T52	6577	0	0	0
T123	47448	63	0	0
T176	0	16	0	0
T177	0	31	0	0
T178	0	67	0	0
T179	0	25	0	0
T180	0	57	0	0
T181	0	47	0	0
T182	0	14	0	0
T183	0	32	0	0
T184	0	18	0	0
T185	1487	0	0	0
T186	5862	0	0	0
T187	3488	0	0	0
T188	5211	0	0	0
T189	7286	0	0	0
T190	89891	0	0	0
T191	10264	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22843288	2842	0	0
T42	4388	0	0	0
T52	6577	0	0	0
T123	47448	34	0	0
T176	0	11	0	0
T177	0	34	0	0
T178	0	43	0	0
T179	0	25	0	0
T180	0	53	0	0
T181	0	32	0	0
T182	0	31	0	0
T183	0	31	0	0
T184	0	16	0	0
T185	1487	0	0	0
T186	5862	0	0	0
T187	3488	0	0	0
T188	5211	0	0	0
T189	7286	0	0	0
T190	89891	0	0	0
T191	10264	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22843288	2818	0	0
T42	4388	0	0	0
T52	6577	0	0	0
T123	47448	44	0	0
T176	0	9	0	0
T177	0	34	0	0
T178	0	38	0	0
T179	0	40	0	0
T180	0	43	0	0
T181	0	17	0	0
T182	0	47	0	0
T183	0	23	0	0
T184	0	16	0	0
T185	1487	0	0	0
T186	5862	0	0	0
T187	3488	0	0	0
T188	5211	0	0	0
T189	7286	0	0	0
T190	89891	0	0	0
T191	10264	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22843288	2680	0	0
T42	4388	0	0	0
T52	6577	0	0	0
T123	47448	59	0	0
T176	0	4	0	0
T177	0	27	0	0
T178	0	31	0	0
T179	0	36	0	0
T180	0	51	0	0
T181	0	34	0	0
T182	0	47	0	0
T183	0	15	0	0
T184	0	17	0	0
T185	1487	0	0	0
T186	5862	0	0	0
T187	3488	0	0	0
T188	5211	0	0	0
T189	7286	0	0	0
T190	89891	0	0	0
T191	10264	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22843288	2792	0	0
T42	4388	0	0	0
T52	6577	0	0	0
T123	47448	46	0	0
T176	0	22	0	0
T177	0	19	0	0
T178	0	29	0	0
T179	0	26	0	0
T180	0	75	0	0
T181	0	44	0	0
T182	0	30	0	0
T183	0	13	0	0
T184	0	5	0	0
T185	1487	0	0	0
T186	5862	0	0	0
T187	3488	0	0	0
T188	5211	0	0	0
T189	7286	0	0	0
T190	89891	0	0	0
T191	10264	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22843288	2611	0	0
T42	4388	0	0	0
T52	6577	0	0	0
T123	47448	39	0	0
T176	0	14	0	0
T177	0	20	0	0
T178	0	24	0	0
T179	0	28	0	0
T180	0	45	0	0
T181	0	30	0	0
T182	0	32	0	0
T183	0	40	0	0
T184	0	20	0	0
T185	1487	0	0	0
T186	5862	0	0	0
T187	3488	0	0	0
T188	5211	0	0	0
T189	7286	0	0	0
T190	89891	0	0	0
T191	10264	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22843288	2896	0	0
T42	4388	0	0	0
T52	6577	0	0	0
T123	47448	67	0	0
T176	0	20	0	0
T177	0	29	0	0
T178	0	24	0	0
T179	0	26	0	0
T180	0	57	0	0
T181	0	26	0	0
T182	0	35	0	0
T183	0	27	0	0
T185	1487	0	0	0
T186	5862	0	0	0
T187	3488	0	0	0
T188	5211	0	0	0
T189	7286	0	0	0
T190	89891	0	0	0
T191	10264	0	0	0
T192	0	2	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22843288	2770	0	0
T1	7606	3	0	0
T2	15290	0	0	0
T3	11970	0	0	0
T11	4816	0	0	0
T12	8079	0	0	0
T13	1039	0	0	0
T14	5794	0	0	0
T15	8652	0	0	0
T16	4330	0	0	0
T17	6812	0	0	0
T123	0	63	0	0
T176	0	15	0	0
T177	0	24	0	0
T178	0	31	0	0
T179	0	28	0	0
T180	0	36	0	0
T181	0	52	0	0
T182	0	39	0	0
T183	0	36	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22843288	3203	0	0
T25	139969	60	0	0
T26	14694	0	0	0
T36	4464	0	0	0
T48	29440	0	0	0
T49	5518	0	0	0
T53	9513	0	0	0
T61	0	38	0	0
T74	0	20	0	0
T76	0	15	0	0
T85	3372	0	0	0
T105	840	0	0	0
T108	18645	0	0	0
T123	0	76	0	0
T136	12383	0	0	0
T176	0	10	0	0
T177	0	57	0	0
T178	0	44	0	0
T179	0	17	0	0
T193	0	20	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22843288	2831	0	0
T42	4388	0	0	0
T52	6577	0	0	0
T123	47448	59	0	0
T176	0	13	0	0
T177	0	8	0	0
T178	0	33	0	0
T179	0	21	0	0
T180	0	31	0	0
T181	0	40	0	0
T182	0	38	0	0
T183	0	30	0	0
T184	0	7	0	0
T185	1487	0	0	0
T186	5862	0	0	0
T187	3488	0	0	0
T188	5211	0	0	0
T189	7286	0	0	0
T190	89891	0	0	0
T191	10264	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22843288	2669	0	0
T42	4388	0	0	0
T52	6577	0	0	0
T123	47448	48	0	0
T176	0	14	0	0
T177	0	26	0	0
T178	0	35	0	0
T179	0	31	0	0
T180	0	43	0	0
T181	0	34	0	0
T182	0	25	0	0
T183	0	26	0	0
T184	0	15	0	0
T185	1487	0	0	0
T186	5862	0	0	0
T187	3488	0	0	0
T188	5211	0	0	0
T189	7286	0	0	0
T190	89891	0	0	0
T191	10264	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22843288	2703	0	0
T42	4388	0	0	0
T52	6577	0	0	0
T123	47448	75	0	0
T176	0	2	0	0
T177	0	36	0	0
T178	0	33	0	0
T179	0	29	0	0
T180	0	67	0	0
T181	0	39	0	0
T182	0	52	0	0
T183	0	39	0	0
T184	0	17	0	0
T185	1487	0	0	0
T186	5862	0	0	0
T187	3488	0	0	0
T188	5211	0	0	0
T189	7286	0	0	0
T190	89891	0	0	0
T191	10264	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22843288	2706	0	0
T42	4388	0	0	0
T52	6577	0	0	0
T123	47448	76	0	0
T176	0	9	0	0
T177	0	36	0	0
T178	0	30	0	0
T179	0	15	0	0
T180	0	59	0	0
T181	0	21	0	0
T182	0	21	0	0
T183	0	15	0	0
T184	0	16	0	0
T185	1487	0	0	0
T186	5862	0	0	0
T187	3488	0	0	0
T188	5211	0	0	0
T189	7286	0	0	0
T190	89891	0	0	0
T191	10264	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22843288	2637	0	0
T42	4388	0	0	0
T52	6577	0	0	0
T123	47448	42	0	0
T176	0	12	0	0
T177	0	27	0	0
T178	0	26	0	0
T179	0	20	0	0
T180	0	52	0	0
T181	0	34	0	0
T182	0	38	0	0
T183	0	33	0	0
T184	0	19	0	0
T185	1487	0	0	0
T186	5862	0	0	0
T187	3488	0	0	0
T188	5211	0	0	0
T189	7286	0	0	0
T190	89891	0	0	0
T191	10264	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22843288	2793	0	0
T42	4388	0	0	0
T52	6577	0	0	0
T123	47448	48	0	0
T176	0	18	0	0
T177	0	15	0	0
T178	0	34	0	0
T179	0	15	0	0
T180	0	55	0	0
T181	0	21	0	0
T182	0	43	0	0
T183	0	13	0	0
T184	0	19	0	0
T185	1487	0	0	0
T186	5862	0	0	0
T187	3488	0	0	0
T188	5211	0	0	0
T189	7286	0	0	0
T190	89891	0	0	0
T191	10264	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22843288	2757	0	0
T42	4388	0	0	0
T52	6577	0	0	0
T123	47448	65	0	0
T176	0	7	0	0
T177	0	25	0	0
T178	0	52	0	0
T179	0	21	0	0
T180	0	32	0	0
T181	0	8	0	0
T182	0	54	0	0
T183	0	21	0	0
T185	1487	0	0	0
T186	5862	0	0	0
T187	3488	0	0	0
T188	5211	0	0	0
T189	7286	0	0	0
T190	89891	0	0	0
T191	10264	0	0	0
T194	0	2	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22843288	2710	0	0
T42	4388	0	0	0
T52	6577	0	0	0
T123	47448	52	0	0
T176	0	5	0	0
T177	0	2	0	0
T178	0	47	0	0
T179	0	20	0	0
T180	0	66	0	0
T181	0	31	0	0
T182	0	23	0	0
T183	0	29	0	0
T184	0	13	0	0
T185	1487	0	0	0
T186	5862	0	0	0
T187	3488	0	0	0
T188	5211	0	0	0
T189	7286	0	0	0
T190	89891	0	0	0
T191	10264	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22843288	2743	0	0
T42	4388	0	0	0
T52	6577	0	0	0
T123	47448	46	0	0
T176	0	3	0	0
T177	0	36	0	0
T178	0	32	0	0
T179	0	21	0	0
T180	0	45	0	0
T181	0	20	0	0
T182	0	17	0	0
T183	0	38	0	0
T184	0	24	0	0
T185	1487	0	0	0
T186	5862	0	0	0
T187	3488	0	0	0
T188	5211	0	0	0
T189	7286	0	0	0
T190	89891	0	0	0
T191	10264	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22843288	2782	0	0
T42	4388	0	0	0
T52	6577	0	0	0
T123	47448	53	0	0
T176	0	12	0	0
T177	0	28	0	0
T178	0	57	0	0
T179	0	25	0	0
T180	0	38	0	0
T181	0	29	0	0
T182	0	22	0	0
T183	0	32	0	0
T185	1487	0	0	0
T186	5862	0	0	0
T187	3488	0	0	0
T188	5211	0	0	0
T189	7286	0	0	0
T190	89891	0	0	0
T191	10264	0	0	0
T195	0	4	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22843288	2773	0	0
T42	4388	0	0	0
T52	6577	0	0	0
T123	47448	45	0	0
T176	0	25	0	0
T177	0	29	0	0
T178	0	52	0	0
T179	0	20	0	0
T180	0	36	0	0
T181	0	39	0	0
T182	0	46	0	0
T183	0	20	0	0
T184	0	9	0	0
T185	1487	0	0	0
T186	5862	0	0	0
T187	3488	0	0	0
T188	5211	0	0	0
T189	7286	0	0	0
T190	89891	0	0	0
T191	10264	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22843288	2665	0	0
T42	4388	0	0	0
T52	6577	0	0	0
T123	47448	64	0	0
T176	0	13	0	0
T177	0	27	0	0
T178	0	37	0	0
T179	0	19	0	0
T180	0	51	0	0
T181	0	65	0	0
T182	0	38	0	0
T183	0	27	0	0
T184	0	10	0	0
T185	1487	0	0	0
T186	5862	0	0	0
T187	3488	0	0	0
T188	5211	0	0	0
T189	7286	0	0	0
T190	89891	0	0	0
T191	10264	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22843288	2777	0	0
T42	4388	0	0	0
T52	6577	0	0	0
T123	47448	51	0	0
T176	0	8	0	0
T177	0	23	0	0
T178	0	10	0	0
T179	0	41	0	0
T180	0	50	0	0
T181	0	21	0	0
T182	0	50	0	0
T183	0	22	0	0
T184	0	43	0	0
T185	1487	0	0	0
T186	5862	0	0	0
T187	3488	0	0	0
T188	5211	0	0	0
T189	7286	0	0	0
T190	89891	0	0	0
T191	10264	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22843288	2719	0	0
T42	4388	0	0	0
T52	6577	0	0	0
T123	47448	44	0	0
T176	0	21	0	0
T177	0	26	0	0
T178	0	46	0	0
T179	0	36	0	0
T180	0	26	0	0
T181	0	22	0	0
T182	0	66	0	0
T183	0	24	0	0
T184	0	25	0	0
T185	1487	0	0	0
T186	5862	0	0	0
T187	3488	0	0	0
T188	5211	0	0	0
T189	7286	0	0	0
T190	89891	0	0	0
T191	10264	0	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22843288	2711	0	0
T42	4388	0	0	0
T52	6577	0	0	0
T123	47448	68	0	0
T176	0	31	0	0
T177	0	12	0	0
T178	0	31	0	0
T179	0	41	0	0
T180	0	51	0	0
T181	0	40	0	0
T182	0	39	0	0
T183	0	22	0	0
T184	0	12	0	0
T185	1487	0	0	0
T186	5862	0	0	0
T187	3488	0	0	0
T188	5211	0	0	0
T189	7286	0	0	0
T190	89891	0	0	0
T191	10264	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22843288	2600	0	0
T42	4388	0	0	0
T52	6577	0	0	0
T123	47448	45	0	0
T176	0	8	0	0
T177	0	36	0	0
T178	0	43	0	0
T179	0	22	0	0
T180	0	26	0	0
T181	0	31	0	0
T182	0	40	0	0
T183	0	19	0	0
T184	0	8	0	0
T185	1487	0	0	0
T186	5862	0	0	0
T187	3488	0	0	0
T188	5211	0	0	0
T189	7286	0	0	0
T190	89891	0	0	0
T191	10264	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22843288	2879	0	0
T42	4388	0	0	0
T52	6577	0	0	0
T123	47448	46	0	0
T176	0	18	0	0
T177	0	31	0	0
T178	0	41	0	0
T179	0	28	0	0
T180	0	55	0	0
T181	0	24	0	0
T182	0	34	0	0
T183	0	29	0	0
T184	0	22	0	0
T185	1487	0	0	0
T186	5862	0	0	0
T187	3488	0	0	0
T188	5211	0	0	0
T189	7286	0	0	0
T190	89891	0	0	0
T191	10264	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22843288	2756	0	0
T42	4388	0	0	0
T52	6577	0	0	0
T123	47448	63	0	0
T176	0	16	0	0
T177	0	47	0	0
T178	0	40	0	0
T179	0	20	0	0
T180	0	57	0	0
T181	0	24	0	0
T182	0	28	0	0
T183	0	37	0	0
T184	0	5	0	0
T185	1487	0	0	0
T186	5862	0	0	0
T187	3488	0	0	0
T188	5211	0	0	0
T189	7286	0	0	0
T190	89891	0	0	0
T191	10264	0	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22843288	2716	0	0
T42	4388	0	0	0
T52	6577	0	0	0
T123	47448	46	0	0
T176	0	14	0	0
T177	0	26	0	0
T178	0	39	0	0
T179	0	22	0	0
T180	0	27	0	0
T181	0	45	0	0
T182	0	20	0	0
T183	0	54	0	0
T184	0	8	0	0
T185	1487	0	0	0
T186	5862	0	0	0
T187	3488	0	0	0
T188	5211	0	0	0
T189	7286	0	0	0
T190	89891	0	0	0
T191	10264	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22843288	2773	0	0
T42	4388	0	0	0
T52	6577	0	0	0
T123	47448	24	0	0
T176	0	13	0	0
T177	0	20	0	0
T178	0	29	0	0
T179	0	31	0	0
T180	0	47	0	0
T181	0	46	0	0
T182	0	37	0	0
T183	0	9	0	0
T184	0	6	0	0
T185	1487	0	0	0
T186	5862	0	0	0
T187	3488	0	0	0
T188	5211	0	0	0
T189	7286	0	0	0
T190	89891	0	0	0
T191	10264	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22843288	2703	0	0
T42	4388	0	0	0
T52	6577	0	0	0
T123	47448	57	0	0
T176	0	10	0	0
T177	0	21	0	0
T178	0	43	0	0
T179	0	27	0	0
T180	0	43	0	0
T181	0	27	0	0
T182	0	33	0	0
T183	0	33	0	0
T184	0	18	0	0
T185	1487	0	0	0
T186	5862	0	0	0
T187	3488	0	0	0
T188	5211	0	0	0
T189	7286	0	0	0
T190	89891	0	0	0
T191	10264	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22843288	2736	0	0
T42	4388	0	0	0
T52	6577	0	0	0
T123	47448	43	0	0
T176	0	20	0	0
T177	0	38	0	0
T178	0	33	0	0
T179	0	32	0	0
T180	0	65	0	0
T181	0	30	0	0
T182	0	49	0	0
T183	0	26	0	0
T184	0	26	0	0
T185	1487	0	0	0
T186	5862	0	0	0
T187	3488	0	0	0
T188	5211	0	0	0
T189	7286	0	0	0
T190	89891	0	0	0
T191	10264	0	0	0