Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3022165	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

616131

1

T1

391

T2

500

T3

484

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3217030	1			T1	313		T2	1400		T3	942
values[0x0]	209805	1			T1	182		T2	174		T3	138
values[0x1]	211461	1			T1	158		T2	200		T3	125

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2072809	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1565487

1

T1

456

T2

889

T3

656

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	13686	1			T11	2		T13	2		T15	3
valid_sources[0x01]	10619	1			T11	6		T15	1		T16	3
valid_sources[0x02]	11999	1			T2	80		T10	6		T11	1
valid_sources[0x03]	11929	1			T10	3		T11	1		T15	6
valid_sources[0x04]	15857	1			T10	24		T11	5		T13	3
valid_sources[0x05]	11003	1			T11	3		T15	6		T16	5
valid_sources[0x06]	10371	1			T11	8		T12	10		T13	2
valid_sources[0x07]	11154	1			T2	47		T10	7		T11	5
valid_sources[0x08]	10467	1			T2	15		T11	8		T12	46
valid_sources[0x09]	12173	1			T11	8		T15	6		T16	4
valid_sources[0x0a]	16177	1			T11	5		T15	4		T16	2
valid_sources[0x0b]	17186	1			T2	52		T11	2		T15	6
valid_sources[0x0c]	12171	1			T11	8		T15	1		T16	3
valid_sources[0x0d]	11154	1			T11	5		T12	5		T15	1
valid_sources[0x0e]	11157	1			T11	4		T12	22		T15	3
valid_sources[0x0f]	15587	1			T11	4		T15	4		T16	5
valid_sources[0x10]	21122	1			T10	6		T11	4		T15	1
valid_sources[0x11]	12977	1			T2	31		T11	5		T15	3
valid_sources[0x12]	12458	1			T11	8		T15	1		T16	6
valid_sources[0x13]	15375	1			T2	4		T11	3		T15	6
valid_sources[0x14]	11561	1			T11	8		T15	3		T16	3
valid_sources[0x15]	11182	1			T11	4		T15	3		T16	5
valid_sources[0x16]	11324	1			T2	26		T11	4		T15	4
valid_sources[0x17]	30590	1			T2	71		T11	5		T15	2
valid_sources[0x18]	11077	1			T11	2		T15	2		T16	3
valid_sources[0x19]	13295	1			T2	5		T11	3		T15	4
valid_sources[0x1a]	10778	1			T2	41		T11	1		T15	3
valid_sources[0x1b]	11217	1			T11	7		T13	43		T15	2
valid_sources[0x1c]	142292	1			T11	4		T12	12		T13	2
valid_sources[0x1d]	11105	1			T2	17		T11	6		T13	107
valid_sources[0x1e]	11702	1			T10	6		T11	7		T12	22
valid_sources[0x1f]	11873	1			T11	5		T15	2		T16	2
valid_sources[0x20]	13504	1			T2	4		T11	6		T12	27
valid_sources[0x21]	13615	1			T11	4		T13	2		T15	4
valid_sources[0x22]	10949	1			T2	141		T11	5		T13	4
valid_sources[0x23]	10323	1			T2	45		T11	3		T13	2
valid_sources[0x24]	14356	1			T2	76		T11	2		T15	7
valid_sources[0x25]	11603	1			T11	5		T15	3		T16	6
valid_sources[0x26]	10410	1			T11	3		T12	8		T15	2
valid_sources[0x27]	11144	1			T2	4		T11	2		T13	4
valid_sources[0x28]	11323	1			T2	4		T11	2		T15	3
valid_sources[0x29]	14172	1			T10	1		T11	1		T15	3
valid_sources[0x2a]	144322	1			T2	4		T11	8		T12	19
valid_sources[0x2b]	10910	1			T11	14		T13	2		T15	1
valid_sources[0x2c]	11437	1			T2	4		T11	1		T13	2
valid_sources[0x2d]	16640	1			T2	4		T11	3		T15	3
valid_sources[0x2e]	11166	1			T11	7		T15	2		T16	3
valid_sources[0x2f]	11395	1			T10	3		T11	10		T13	637
valid_sources[0x30]	23251	1			T2	51		T11	3		T13	2
valid_sources[0x31]	10233	1			T2	4		T11	9		T16	3
valid_sources[0x32]	14004	1			T11	7		T15	8		T34	3
valid_sources[0x33]	21808	1			T11	1		T15	3		T16	2
valid_sources[0x34]	11764	1			T2	9		T10	10		T11	7
valid_sources[0x35]	15216	1			T11	6		T13	2		T15	4
valid_sources[0x36]	11958	1			T11	3		T15	1		T16	8
valid_sources[0x37]	10908	1			T10	20		T11	5		T15	4
valid_sources[0x38]	13385	1			T10	8		T11	7		T15	9
valid_sources[0x39]	13256	1			T2	18		T11	3		T13	23
valid_sources[0x3a]	37921	1			T11	14		T16	3		T34	6
valid_sources[0x3b]	12368	1			T11	4		T15	10		T16	6
valid_sources[0x3c]	15622	1			T11	7		T13	2		T15	5
valid_sources[0x3d]	11676	1			T11	3		T15	2		T16	2
valid_sources[0x3e]	13007	1			T2	3		T11	1		T15	3
valid_sources[0x3f]	11752	1			T11	5		T15	2		T16	1
valid_sources[0x40]	11892	1			T11	9		T15	1		T16	3
valid_sources[0x41]	10298	1			T11	12		T15	7		T34	4
valid_sources[0x42]	11025	1			T2	67		T11	4		T15	3
valid_sources[0x43]	11206	1			T10	1		T11	12		T15	3
valid_sources[0x44]	10738	1			T2	4		T11	6		T12	6
valid_sources[0x45]	14924	1			T10	7		T11	5		T13	2
valid_sources[0x46]	11068	1			T10	38		T11	3		T15	1
valid_sources[0x47]	10793	1			T10	5		T11	5		T15	2
valid_sources[0x48]	13496	1			T11	8		T15	1		T16	1
valid_sources[0x49]	9910	1			T11	7		T16	1		T34	1
valid_sources[0x4a]	12400	1			T10	3		T11	1		T15	2
valid_sources[0x4b]	12048	1			T2	1		T11	6		T12	12
valid_sources[0x4c]	11864	1			T11	2		T15	7		T16	1
valid_sources[0x4d]	14351	1			T11	6		T15	2		T16	4
valid_sources[0x4e]	10544	1			T2	7		T11	2		T15	5
valid_sources[0x4f]	10985	1			T11	7		T15	6		T16	5
valid_sources[0x50]	13766	1			T2	19		T11	6		T15	1
valid_sources[0x51]	12352	1			T2	30		T11	2		T15	2
valid_sources[0x52]	12206	1			T11	4		T15	2		T16	1
valid_sources[0x53]	12409	1			T11	5		T12	9		T15	1
valid_sources[0x54]	10464	1			T11	2		T12	23		T15	1
valid_sources[0x55]	14563	1			T11	4		T12	23		T15	5
valid_sources[0x56]	11492	1			T11	2		T16	4		T34	7
valid_sources[0x57]	12252	1			T2	3		T10	2		T11	4
valid_sources[0x58]	13901	1			T10	3		T11	3		T16	2
valid_sources[0x59]	12749	1			T11	2		T16	3		T34	2
valid_sources[0x5a]	12247	1			T2	5		T11	4		T15	2
valid_sources[0x5b]	10146	1			T10	6		T11	9		T15	1
valid_sources[0x5c]	11591	1			T11	2		T12	11		T15	5
valid_sources[0x5d]	10581	1			T11	4		T15	2		T16	5
valid_sources[0x5e]	10763	1			T11	8		T15	3		T16	4
valid_sources[0x5f]	12041	1			T11	3		T15	1		T16	3
valid_sources[0x60]	21278	1			T2	3		T11	2		T15	1
valid_sources[0x61]	11558	1			T10	13		T11	8		T12	9
valid_sources[0x62]	13125	1			T11	8		T12	18		T15	1
valid_sources[0x63]	12362	1			T11	5		T15	1		T16	5
valid_sources[0x64]	10836	1			T11	5		T16	2		T34	1
valid_sources[0x65]	13503	1			T2	1		T11	2		T15	9
valid_sources[0x66]	14334	1			T11	7		T15	1		T16	2
valid_sources[0x67]	10913	1			T2	3		T11	7		T13	2
valid_sources[0x68]	13523	1			T11	5		T12	20		T15	4
valid_sources[0x69]	10963	1			T10	9		T11	4		T12	13
valid_sources[0x6a]	17003	1			T12	2		T13	2		T15	2
valid_sources[0x6b]	12215	1			T10	15		T11	4		T15	2
valid_sources[0x6c]	12696	1			T11	9		T15	2		T16	3
valid_sources[0x6d]	10398	1			T10	8		T11	5		T15	4
valid_sources[0x6e]	11860	1			T10	3		T11	5		T15	6
valid_sources[0x6f]	11790	1			T10	14		T11	3		T15	1
valid_sources[0x70]	13485	1			T11	3		T15	2		T16	2
valid_sources[0x71]	11274	1			T11	5		T15	1		T16	2
valid_sources[0x72]	11242	1			T2	68		T10	8		T11	5
valid_sources[0x73]	12061	1			T10	9		T11	9		T15	2
valid_sources[0x74]	12574	1			T10	15		T11	2		T15	3
valid_sources[0x75]	12505	1			T11	8		T12	5		T15	4
valid_sources[0x76]	11566	1			T11	8		T13	2		T15	2
valid_sources[0x77]	23221	1			T11	4		T15	3		T16	1
valid_sources[0x78]	25438	1			T11	3		T15	7		T16	3
valid_sources[0x79]	10732	1			T11	9		T15	6		T16	10
valid_sources[0x7a]	12147	1			T10	19		T11	6		T15	6
valid_sources[0x7b]	11282	1			T2	14		T11	8		T15	6
valid_sources[0x7c]	11142	1			T11	7		T15	1		T16	5
valid_sources[0x7d]	13513	1			T11	3		T15	4		T16	6
valid_sources[0x7e]	15342	1			T2	3		T10	5		T11	3
valid_sources[0x7f]	49467	1			T2	29		T11	5		T15	1
valid_sources[0x80]	25738	1			T11	1		T15	2		T16	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

328296

1

T1

131

T2

236

T3

310

values[0x0]

all_enables

biggest_size

151517

1

T1

140

T2

129

T3

96

values[0x1]

all_enables

biggest_size

136318

1

T1

120

T2

135

T3

78