Toggle Coverage for Module :
prim_secded_inv_72_64_dec
| Total | Covered | Percent |
Totals |
4 |
3 |
75.00 |
Total Bits |
292 |
290 |
99.32 |
Total Bits 0->1 |
146 |
145 |
99.32 |
Total Bits 1->0 |
146 |
145 |
99.32 |
| | | |
Ports |
4 |
3 |
75.00 |
Port Bits |
292 |
290 |
99.32 |
Port Bits 0->1 |
146 |
145 |
99.32 |
Port Bits 1->0 |
146 |
145 |
99.32 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[71:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
data_o[63:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
syndrome_o[7:0] |
Yes |
Yes |
T62,T134,T135 |
Yes |
T62,T134,T135 |
OUTPUT |
err_o[0] |
Yes |
Yes |
*T136,*T137,*T62 |
Yes |
T136,T137,T62 |
OUTPUT |
err_o[1] |
No |
No |
|
No |
|
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[1].u_dec
| Total | Covered | Percent |
Totals |
4 |
2 |
50.00 |
Total Bits |
292 |
272 |
93.15 |
Total Bits 0->1 |
146 |
136 |
93.15 |
Total Bits 1->0 |
146 |
136 |
93.15 |
| | | |
Ports |
4 |
2 |
50.00 |
Port Bits |
292 |
272 |
93.15 |
Port Bits 0->1 |
146 |
136 |
93.15 |
Port Bits 1->0 |
146 |
136 |
93.15 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[71:0] |
Yes |
Yes |
T1,T2,T12 |
Yes |
T1,T2,T10 |
INPUT |
data_o[63:0] |
Yes |
Yes |
T1,T2,T12 |
Yes |
T1,T2,T10 |
OUTPUT |
syndrome_o[7:0] |
No |
No |
|
No |
|
OUTPUT |
err_o[1:0] |
No |
No |
|
No |
|
OUTPUT |
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[1].u_dec
| Total | Covered | Percent |
Totals |
4 |
2 |
50.00 |
Total Bits |
292 |
272 |
93.15 |
Total Bits 0->1 |
146 |
136 |
93.15 |
Total Bits 1->0 |
146 |
136 |
93.15 |
| | | |
Ports |
4 |
2 |
50.00 |
Port Bits |
292 |
272 |
93.15 |
Port Bits 0->1 |
146 |
136 |
93.15 |
Port Bits 1->0 |
146 |
136 |
93.15 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[71:0] |
Yes |
Yes |
T1,T2,T10 |
Yes |
T1,T2,T10 |
INPUT |
data_o[63:0] |
Yes |
Yes |
T1,T2,T10 |
Yes |
T1,T2,T10 |
OUTPUT |
syndrome_o[7:0] |
No |
No |
|
No |
|
OUTPUT |
err_o[1:0] |
No |
No |
|
No |
|
OUTPUT |
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[2].u_dec
| Total | Covered | Percent |
Totals |
4 |
2 |
50.00 |
Total Bits |
292 |
272 |
93.15 |
Total Bits 0->1 |
146 |
136 |
93.15 |
Total Bits 1->0 |
146 |
136 |
93.15 |
| | | |
Ports |
4 |
2 |
50.00 |
Port Bits |
292 |
272 |
93.15 |
Port Bits 0->1 |
146 |
136 |
93.15 |
Port Bits 1->0 |
146 |
136 |
93.15 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[71:0] |
Yes |
Yes |
T1,T2,T11 |
Yes |
T1,T2,T10 |
INPUT |
data_o[63:0] |
Yes |
Yes |
T1,T2,T11 |
Yes |
T1,T2,T10 |
OUTPUT |
syndrome_o[7:0] |
No |
No |
|
No |
|
OUTPUT |
err_o[1:0] |
No |
No |
|
No |
|
OUTPUT |
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[1].u_dec
| Total | Covered | Percent |
Totals |
4 |
2 |
50.00 |
Total Bits |
292 |
272 |
93.15 |
Total Bits 0->1 |
146 |
136 |
93.15 |
Total Bits 1->0 |
146 |
136 |
93.15 |
| | | |
Ports |
4 |
2 |
50.00 |
Port Bits |
292 |
272 |
93.15 |
Port Bits 0->1 |
146 |
136 |
93.15 |
Port Bits 1->0 |
146 |
136 |
93.15 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[71:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
data_o[63:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
syndrome_o[7:0] |
No |
No |
|
No |
|
OUTPUT |
err_o[1:0] |
No |
No |
|
No |
|
OUTPUT |
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[2].u_dec
| Total | Covered | Percent |
Totals |
4 |
2 |
50.00 |
Total Bits |
292 |
272 |
93.15 |
Total Bits 0->1 |
146 |
136 |
93.15 |
Total Bits 1->0 |
146 |
136 |
93.15 |
| | | |
Ports |
4 |
2 |
50.00 |
Port Bits |
292 |
272 |
93.15 |
Port Bits 0->1 |
146 |
136 |
93.15 |
Port Bits 1->0 |
146 |
136 |
93.15 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[71:0] |
Yes |
Yes |
T1,T2,T12 |
Yes |
T1,T2,T3 |
INPUT |
data_o[63:0] |
Yes |
Yes |
T1,T2,T12 |
Yes |
T1,T2,T3 |
OUTPUT |
syndrome_o[7:0] |
No |
No |
|
No |
|
OUTPUT |
err_o[1:0] |
No |
No |
|
No |
|
OUTPUT |
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[0].u_dec
| Total | Covered | Percent |
Totals |
4 |
2 |
50.00 |
Total Bits |
292 |
280 |
95.89 |
Total Bits 0->1 |
146 |
140 |
95.89 |
Total Bits 1->0 |
146 |
140 |
95.89 |
| | | |
Ports |
4 |
2 |
50.00 |
Port Bits |
292 |
280 |
95.89 |
Port Bits 0->1 |
146 |
140 |
95.89 |
Port Bits 1->0 |
146 |
140 |
95.89 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[71:0] |
Yes |
Yes |
T1,T2,T10 |
Yes |
T1,T2,T3 |
INPUT |
data_o[63:0] |
Yes |
Yes |
T1,T2,T10 |
Yes |
T1,T2,T3 |
OUTPUT |
syndrome_o[0] |
Yes |
Yes |
*T135 |
Yes |
T135 |
OUTPUT |
syndrome_o[2:1] |
No |
No |
|
No |
|
OUTPUT |
syndrome_o[3] |
Yes |
Yes |
*T135 |
Yes |
T135 |
OUTPUT |
syndrome_o[5:4] |
No |
No |
|
No |
|
OUTPUT |
syndrome_o[6] |
Yes |
Yes |
*T135 |
Yes |
T135 |
OUTPUT |
syndrome_o[7] |
No |
No |
|
No |
|
OUTPUT |
err_o[0] |
Yes |
Yes |
*T135 |
Yes |
T135 |
OUTPUT |
err_o[1] |
No |
No |
|
No |
|
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[3].u_dec
| Total | Covered | Percent |
Totals |
4 |
2 |
50.00 |
Total Bits |
292 |
280 |
95.89 |
Total Bits 0->1 |
146 |
140 |
95.89 |
Total Bits 1->0 |
146 |
140 |
95.89 |
| | | |
Ports |
4 |
2 |
50.00 |
Port Bits |
292 |
280 |
95.89 |
Port Bits 0->1 |
146 |
140 |
95.89 |
Port Bits 1->0 |
146 |
140 |
95.89 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[71:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
data_o[63:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
syndrome_o[1:0] |
No |
No |
|
No |
|
OUTPUT |
syndrome_o[2] |
Yes |
Yes |
*T138 |
Yes |
T138 |
OUTPUT |
syndrome_o[4:3] |
No |
No |
|
No |
|
OUTPUT |
syndrome_o[5] |
Yes |
Yes |
*T138 |
Yes |
T138 |
OUTPUT |
syndrome_o[6] |
No |
No |
|
No |
|
OUTPUT |
syndrome_o[7] |
Yes |
Yes |
T138 |
Yes |
T138 |
OUTPUT |
err_o[0] |
Yes |
Yes |
*T138 |
Yes |
T138 |
OUTPUT |
err_o[1] |
No |
No |
|
No |
|
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[0].u_dec
| Total | Covered | Percent |
Totals |
4 |
2 |
50.00 |
Total Bits |
292 |
280 |
95.89 |
Total Bits 0->1 |
146 |
140 |
95.89 |
Total Bits 1->0 |
146 |
140 |
95.89 |
| | | |
Ports |
4 |
2 |
50.00 |
Port Bits |
292 |
280 |
95.89 |
Port Bits 0->1 |
146 |
140 |
95.89 |
Port Bits 1->0 |
146 |
140 |
95.89 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[71:0] |
Yes |
Yes |
T1,T2,T10 |
Yes |
T1,T2,T3 |
INPUT |
data_o[63:0] |
Yes |
Yes |
T1,T2,T10 |
Yes |
T1,T2,T3 |
OUTPUT |
syndrome_o[0] |
No |
No |
|
No |
|
OUTPUT |
syndrome_o[3:1] |
Yes |
Yes |
T139 |
Yes |
T139 |
OUTPUT |
syndrome_o[7:4] |
No |
No |
|
No |
|
OUTPUT |
err_o[0] |
Yes |
Yes |
*T139 |
Yes |
T139 |
OUTPUT |
err_o[1] |
No |
No |
|
No |
|
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[1].u_dec
| Total | Covered | Percent |
Totals |
4 |
2 |
50.00 |
Total Bits |
292 |
280 |
95.89 |
Total Bits 0->1 |
146 |
140 |
95.89 |
Total Bits 1->0 |
146 |
140 |
95.89 |
| | | |
Ports |
4 |
2 |
50.00 |
Port Bits |
292 |
280 |
95.89 |
Port Bits 0->1 |
146 |
140 |
95.89 |
Port Bits 1->0 |
146 |
140 |
95.89 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[71:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
data_o[63:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
syndrome_o[1:0] |
No |
No |
|
No |
|
OUTPUT |
syndrome_o[3:2] |
Yes |
Yes |
T138 |
Yes |
T138 |
OUTPUT |
syndrome_o[5:4] |
No |
No |
|
No |
|
OUTPUT |
syndrome_o[6] |
Yes |
Yes |
*T138 |
Yes |
T138 |
OUTPUT |
syndrome_o[7] |
No |
No |
|
No |
|
OUTPUT |
err_o[0] |
Yes |
Yes |
*T138 |
Yes |
T138 |
OUTPUT |
err_o[1] |
No |
No |
|
No |
|
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[2].u_dec
| Total | Covered | Percent |
Totals |
4 |
2 |
50.00 |
Total Bits |
292 |
280 |
95.89 |
Total Bits 0->1 |
146 |
140 |
95.89 |
Total Bits 1->0 |
146 |
140 |
95.89 |
| | | |
Ports |
4 |
2 |
50.00 |
Port Bits |
292 |
280 |
95.89 |
Port Bits 0->1 |
146 |
140 |
95.89 |
Port Bits 1->0 |
146 |
140 |
95.89 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[71:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
data_o[63:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
syndrome_o[0] |
No |
No |
|
No |
|
OUTPUT |
syndrome_o[2:1] |
Yes |
Yes |
T140 |
Yes |
T140 |
OUTPUT |
syndrome_o[6:3] |
No |
No |
|
No |
|
OUTPUT |
syndrome_o[7] |
Yes |
Yes |
T140 |
Yes |
T140 |
OUTPUT |
err_o[0] |
Yes |
Yes |
*T140 |
Yes |
T140 |
OUTPUT |
err_o[1] |
No |
No |
|
No |
|
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[3].u_dec
| Total | Covered | Percent |
Totals |
4 |
2 |
50.00 |
Total Bits |
292 |
280 |
95.89 |
Total Bits 0->1 |
146 |
140 |
95.89 |
Total Bits 1->0 |
146 |
140 |
95.89 |
| | | |
Ports |
4 |
2 |
50.00 |
Port Bits |
292 |
280 |
95.89 |
Port Bits 0->1 |
146 |
140 |
95.89 |
Port Bits 1->0 |
146 |
140 |
95.89 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[71:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
data_o[63:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
syndrome_o[0] |
Yes |
Yes |
*T141 |
Yes |
T141 |
OUTPUT |
syndrome_o[3:1] |
No |
No |
|
No |
|
OUTPUT |
syndrome_o[4] |
Yes |
Yes |
*T141 |
Yes |
T141 |
OUTPUT |
syndrome_o[6:5] |
No |
No |
|
No |
|
OUTPUT |
syndrome_o[7] |
Yes |
Yes |
T141 |
Yes |
T141 |
OUTPUT |
err_o[0] |
Yes |
Yes |
*T141 |
Yes |
T141 |
OUTPUT |
err_o[1] |
No |
No |
|
No |
|
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[0].u_dec
| Total | Covered | Percent |
Totals |
4 |
2 |
50.00 |
Total Bits |
292 |
284 |
97.26 |
Total Bits 0->1 |
146 |
142 |
97.26 |
Total Bits 1->0 |
146 |
142 |
97.26 |
| | | |
Ports |
4 |
2 |
50.00 |
Port Bits |
292 |
284 |
97.26 |
Port Bits 0->1 |
146 |
142 |
97.26 |
Port Bits 1->0 |
146 |
142 |
97.26 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[71:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
data_o[63:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
syndrome_o[0] |
Yes |
Yes |
*T142 |
Yes |
T142 |
OUTPUT |
syndrome_o[2:1] |
No |
No |
|
No |
|
OUTPUT |
syndrome_o[4:3] |
Yes |
Yes |
T142,*T141 |
Yes |
T142,T141 |
OUTPUT |
syndrome_o[5] |
No |
No |
|
No |
|
OUTPUT |
syndrome_o[7:6] |
Yes |
Yes |
T141 |
Yes |
T141 |
OUTPUT |
err_o[0] |
Yes |
Yes |
*T141,*T142 |
Yes |
T141,T142 |
OUTPUT |
err_o[1] |
No |
No |
|
No |
|
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[2].u_dec
| Total | Covered | Percent |
Totals |
4 |
2 |
50.00 |
Total Bits |
292 |
286 |
97.95 |
Total Bits 0->1 |
146 |
143 |
97.95 |
Total Bits 1->0 |
146 |
143 |
97.95 |
| | | |
Ports |
4 |
2 |
50.00 |
Port Bits |
292 |
286 |
97.95 |
Port Bits 0->1 |
146 |
143 |
97.95 |
Port Bits 1->0 |
146 |
143 |
97.95 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[71:0] |
Yes |
Yes |
T1,T2,T10 |
Yes |
T1,T2,T10 |
INPUT |
data_o[63:0] |
Yes |
Yes |
T1,T2,T10 |
Yes |
T1,T2,T10 |
OUTPUT |
syndrome_o[0] |
Yes |
Yes |
*T62,*T140 |
Yes |
T62,T140 |
OUTPUT |
syndrome_o[1] |
No |
No |
|
No |
|
OUTPUT |
syndrome_o[6:2] |
Yes |
Yes |
*T62,*T134,*T140 |
Yes |
T62,T134,T140 |
OUTPUT |
syndrome_o[7] |
No |
No |
|
No |
|
OUTPUT |
err_o[0] |
Yes |
Yes |
*T62,*T134,*T140 |
Yes |
T62,T134,T140 |
OUTPUT |
err_o[1] |
No |
No |
|
No |
|
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[3].u_dec
| Total | Covered | Percent |
Totals |
4 |
2 |
50.00 |
Total Bits |
292 |
286 |
97.95 |
Total Bits 0->1 |
146 |
143 |
97.95 |
Total Bits 1->0 |
146 |
143 |
97.95 |
| | | |
Ports |
4 |
2 |
50.00 |
Port Bits |
292 |
286 |
97.95 |
Port Bits 0->1 |
146 |
143 |
97.95 |
Port Bits 1->0 |
146 |
143 |
97.95 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[71:0] |
Yes |
Yes |
T1,T2,T10 |
Yes |
T1,T2,T3 |
INPUT |
data_o[63:0] |
Yes |
Yes |
T1,T2,T10 |
Yes |
T1,T2,T3 |
OUTPUT |
syndrome_o[0] |
Yes |
Yes |
*T134 |
Yes |
T134 |
OUTPUT |
syndrome_o[1] |
No |
No |
|
No |
|
OUTPUT |
syndrome_o[2] |
Yes |
Yes |
*T139 |
Yes |
T139 |
OUTPUT |
syndrome_o[3] |
No |
No |
|
No |
|
OUTPUT |
syndrome_o[7:4] |
Yes |
Yes |
T134,T139 |
Yes |
T134,T139 |
OUTPUT |
err_o[0] |
Yes |
Yes |
*T134,*T139 |
Yes |
T134,T139 |
OUTPUT |
err_o[1] |
No |
No |
|
No |
|
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[0].u_dec
| Total | Covered | Percent |
Totals |
4 |
2 |
50.00 |
Total Bits |
292 |
286 |
97.95 |
Total Bits 0->1 |
146 |
143 |
97.95 |
Total Bits 1->0 |
146 |
143 |
97.95 |
| | | |
Ports |
4 |
2 |
50.00 |
Port Bits |
292 |
286 |
97.95 |
Port Bits 0->1 |
146 |
143 |
97.95 |
Port Bits 1->0 |
146 |
143 |
97.95 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[71:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
data_o[63:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
syndrome_o[1:0] |
Yes |
Yes |
*T143,*T144,*T136 |
Yes |
T143,T144,T136 |
OUTPUT |
syndrome_o[2] |
No |
No |
|
No |
|
OUTPUT |
syndrome_o[6:3] |
Yes |
Yes |
*T136,T143,T144 |
Yes |
T136,T143,T144 |
OUTPUT |
syndrome_o[7] |
No |
No |
|
No |
|
OUTPUT |
err_o[0] |
Yes |
Yes |
*T136,*T143,*T144 |
Yes |
T136,T143,T144 |
OUTPUT |
err_o[1] |
No |
No |
|
No |
|
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[3].u_dec
| Total | Covered | Percent |
Totals |
4 |
2 |
50.00 |
Total Bits |
292 |
288 |
98.63 |
Total Bits 0->1 |
146 |
144 |
98.63 |
Total Bits 1->0 |
146 |
144 |
98.63 |
| | | |
Ports |
4 |
2 |
50.00 |
Port Bits |
292 |
288 |
98.63 |
Port Bits 0->1 |
146 |
144 |
98.63 |
Port Bits 1->0 |
146 |
144 |
98.63 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[71:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
data_o[63:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
syndrome_o[1:0] |
Yes |
Yes |
*T143,T145 |
Yes |
T143,T145 |
OUTPUT |
syndrome_o[2] |
No |
No |
|
No |
|
OUTPUT |
syndrome_o[7:3] |
Yes |
Yes |
T137,T143,T145 |
Yes |
T137,T143,T145 |
OUTPUT |
err_o[0] |
Yes |
Yes |
*T137,*T143,*T145 |
Yes |
T137,T143,T145 |
OUTPUT |
err_o[1] |
No |
No |
|
No |
|
OUTPUT |
*Tests covering at least one bit in the range