Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	23316540	14256	0	0
attest_sw_binding_0_rd_A	23316540	3067	0	0
attest_sw_binding_1_rd_A	23316540	3420	0	0
attest_sw_binding_2_rd_A	23316540	3315	0	0
attest_sw_binding_3_rd_A	23316540	3453	0	0
attest_sw_binding_4_rd_A	23316540	3263	0	0
attest_sw_binding_5_rd_A	23316540	3063	0	0
attest_sw_binding_6_rd_A	23316540	3424	0	0
attest_sw_binding_7_rd_A	23316540	3384	0	0
intr_enable_rd_A	23316540	4096	0	0
key_version_rd_A	23316540	3519	0	0
max_creator_key_ver_regwen_rd_A	23316540	3405	0	0
max_owner_int_key_ver_regwen_rd_A	23316540	3369	0	0
max_owner_key_ver_regwen_rd_A	23316540	3418	0	0
reseed_interval_regwen_rd_A	23316540	3372	0	0
salt_0_rd_A	23316540	3480	0	0
salt_1_rd_A	23316540	3236	0	0
salt_2_rd_A	23316540	3420	0	0
salt_3_rd_A	23316540	3323	0	0
salt_4_rd_A	23316540	3424	0	0
salt_5_rd_A	23316540	3312	0	0
salt_6_rd_A	23316540	3400	0	0
salt_7_rd_A	23316540	3381	0	0
sealing_sw_binding_0_rd_A	23316540	3318	0	0
sealing_sw_binding_1_rd_A	23316540	3289	0	0
sealing_sw_binding_2_rd_A	23316540	3410	0	0
sealing_sw_binding_3_rd_A	23316540	3300	0	0
sealing_sw_binding_4_rd_A	23316540	3147	0	0
sealing_sw_binding_5_rd_A	23316540	3333	0	0
sealing_sw_binding_6_rd_A	23316540	3335	0	0
sealing_sw_binding_7_rd_A	23316540	3343	0	0
sideload_clear_rd_A	23316540	3326	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23316540	14256	0	0
T4	122904	0	0	0
T37	11248	0	0	0
T49	0	559	0	0
T54	0	175	0	0
T58	0	165	0	0
T67	18009	0	0	0
T88	10675	0	0	0
T93	18774	263	0	0
T99	0	665	0	0
T105	0	23	0	0
T109	0	310	0	0
T114	0	228	0	0
T115	0	228	0	0
T116	0	22	0	0
T117	5176	0	0	0
T118	3105	0	0	0
T119	9497	0	0	0
T120	141641	0	0	0
T121	10168	0	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23316540	3067	0	0
T40	6953	0	0	0
T62	18288	0	0	0
T79	128795	0	0	0
T105	16580	21	0	0
T109	35507	0	0	0
T110	0	22	0	0
T116	0	18	0	0
T147	0	10	0	0
T148	0	8	0	0
T152	0	58	0	0
T153	0	11	0	0
T176	0	60	0	0
T177	0	17	0	0
T178	0	6	0	0
T179	8997	0	0	0
T180	2216	0	0	0
T181	9644	0	0	0
T182	27578	0	0	0
T183	7311	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23316540	3420	0	0
T40	6953	0	0	0
T62	18288	0	0	0
T79	128795	0	0	0
T105	16580	3	0	0
T109	35507	0	0	0
T110	0	25	0	0
T116	0	21	0	0
T147	0	10	0	0
T148	0	15	0	0
T153	0	16	0	0
T176	0	61	0	0
T177	0	9	0	0
T178	0	3	0	0
T179	8997	0	0	0
T180	2216	0	0	0
T181	9644	0	0	0
T182	27578	0	0	0
T183	7311	0	0	0
T184	0	1	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23316540	3315	0	0
T40	6953	0	0	0
T62	18288	0	0	0
T79	128795	0	0	0
T105	16580	23	0	0
T109	35507	0	0	0
T110	0	20	0	0
T116	0	20	0	0
T147	0	9	0	0
T148	0	5	0	0
T153	0	12	0	0
T176	0	56	0	0
T177	0	20	0	0
T178	0	8	0	0
T179	8997	0	0	0
T180	2216	0	0	0
T181	9644	0	0	0
T182	27578	0	0	0
T183	7311	0	0	0
T184	0	7	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23316540	3453	0	0
T5	633269	0	0	0
T28	9064	0	0	0
T36	35264	6	0	0
T52	7861	0	0	0
T54	55205	0	0	0
T55	3700	0	0	0
T91	1108	0	0	0
T105	0	22	0	0
T110	0	24	0	0
T116	0	36	0	0
T147	0	12	0	0
T148	0	8	0	0
T153	0	12	0	0
T176	0	58	0	0
T177	0	55	0	0
T178	0	37	0	0
T185	3883	0	0	0
T186	4087	0	0	0
T187	5008	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23316540	3263	0	0
T40	6953	0	0	0
T62	18288	0	0	0
T79	128795	0	0	0
T105	16580	24	0	0
T109	35507	0	0	0
T110	0	11	0	0
T116	0	35	0	0
T147	0	5	0	0
T148	0	20	0	0
T152	0	77	0	0
T153	0	3	0	0
T176	0	75	0	0
T177	0	32	0	0
T178	0	11	0	0
T179	8997	0	0	0
T180	2216	0	0	0
T181	9644	0	0	0
T182	27578	0	0	0
T183	7311	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23316540	3063	0	0
T40	6953	0	0	0
T62	18288	0	0	0
T79	128795	0	0	0
T105	16580	20	0	0
T109	35507	0	0	0
T110	0	22	0	0
T116	0	35	0	0
T147	0	4	0	0
T148	0	22	0	0
T153	0	13	0	0
T176	0	41	0	0
T177	0	29	0	0
T178	0	9	0	0
T179	8997	0	0	0
T180	2216	0	0	0
T181	9644	0	0	0
T182	27578	0	0	0
T183	7311	0	0	0
T184	0	4	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23316540	3424	0	0
T40	6953	0	0	0
T62	18288	0	0	0
T79	128795	0	0	0
T105	16580	36	0	0
T109	35507	0	0	0
T110	0	14	0	0
T116	0	10	0	0
T147	0	5	0	0
T148	0	14	0	0
T153	0	14	0	0
T176	0	62	0	0
T177	0	36	0	0
T178	0	17	0	0
T179	8997	0	0	0
T180	2216	0	0	0
T181	9644	0	0	0
T182	27578	0	0	0
T183	7311	0	0	0
T184	0	9	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23316540	3384	0	0
T40	6953	0	0	0
T62	18288	0	0	0
T79	128795	0	0	0
T105	16580	18	0	0
T109	35507	0	0	0
T110	0	14	0	0
T116	0	40	0	0
T147	0	12	0	0
T148	0	9	0	0
T153	0	13	0	0
T176	0	57	0	0
T177	0	39	0	0
T178	0	21	0	0
T179	8997	0	0	0
T180	2216	0	0	0
T181	9644	0	0	0
T182	27578	0	0	0
T183	7311	0	0	0
T184	0	9	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23316540	4096	0	0
T38	4259	0	0	0
T46	160711	3	0	0
T50	0	36	0	0
T59	6625	0	0	0
T69	0	42	0	0
T105	0	66	0	0
T116	0	35	0	0
T176	0	127	0	0
T177	0	46	0	0
T188	0	31	0	0
T189	0	5	0	0
T190	0	15	0	0
T191	18309	0	0	0
T192	4567	0	0	0
T193	7852	0	0	0
T194	8426	0	0	0
T195	31067	0	0	0
T196	5238	0	0	0
T197	5748	0	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23316540	3519	0	0
T40	6953	0	0	0
T62	18288	0	0	0
T79	128795	0	0	0
T105	16580	19	0	0
T109	35507	0	0	0
T110	0	19	0	0
T116	0	22	0	0
T147	0	5	0	0
T148	0	36	0	0
T152	0	68	0	0
T153	0	16	0	0
T176	0	75	0	0
T177	0	54	0	0
T178	0	8	0	0
T179	8997	0	0	0
T180	2216	0	0	0
T181	9644	0	0	0
T182	27578	0	0	0
T183	7311	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23316540	3405	0	0
T40	6953	0	0	0
T62	18288	0	0	0
T79	128795	0	0	0
T105	16580	25	0	0
T109	35507	0	0	0
T110	0	20	0	0
T116	0	36	0	0
T147	0	12	0	0
T148	0	23	0	0
T153	0	6	0	0
T176	0	52	0	0
T177	0	54	0	0
T178	0	12	0	0
T179	8997	0	0	0
T180	2216	0	0	0
T181	9644	0	0	0
T182	27578	0	0	0
T183	7311	0	0	0
T184	0	2	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23316540	3369	0	0
T40	6953	0	0	0
T62	18288	0	0	0
T79	128795	0	0	0
T105	16580	32	0	0
T109	35507	0	0	0
T110	0	15	0	0
T116	0	26	0	0
T147	0	3	0	0
T148	0	25	0	0
T153	0	11	0	0
T176	0	44	0	0
T177	0	38	0	0
T178	0	19	0	0
T179	8997	0	0	0
T180	2216	0	0	0
T181	9644	0	0	0
T182	27578	0	0	0
T183	7311	0	0	0
T184	0	20	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23316540	3418	0	0
T40	6953	0	0	0
T62	18288	0	0	0
T79	128795	0	0	0
T105	16580	15	0	0
T109	35507	0	0	0
T110	0	20	0	0
T116	0	19	0	0
T147	0	5	0	0
T148	0	22	0	0
T153	0	11	0	0
T176	0	77	0	0
T177	0	50	0	0
T178	0	27	0	0
T179	8997	0	0	0
T180	2216	0	0	0
T181	9644	0	0	0
T182	27578	0	0	0
T183	7311	0	0	0
T184	0	5	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23316540	3372	0	0
T40	6953	0	0	0
T62	18288	0	0	0
T79	128795	0	0	0
T105	16580	24	0	0
T109	35507	0	0	0
T110	0	10	0	0
T116	0	32	0	0
T147	0	8	0	0
T148	0	17	0	0
T153	0	10	0	0
T176	0	58	0	0
T177	0	9	0	0
T178	0	25	0	0
T179	8997	0	0	0
T180	2216	0	0	0
T181	9644	0	0	0
T182	27578	0	0	0
T183	7311	0	0	0
T184	0	5	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23316540	3480	0	0
T40	6953	0	0	0
T62	18288	0	0	0
T79	128795	0	0	0
T105	16580	28	0	0
T109	35507	0	0	0
T110	0	20	0	0
T116	0	32	0	0
T147	0	9	0	0
T148	0	12	0	0
T153	0	2	0	0
T176	0	66	0	0
T177	0	41	0	0
T178	0	6	0	0
T179	8997	0	0	0
T180	2216	0	0	0
T181	9644	0	0	0
T182	27578	0	0	0
T183	7311	0	0	0
T184	0	2	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23316540	3236	0	0
T40	6953	0	0	0
T62	18288	0	0	0
T79	128795	0	0	0
T105	16580	13	0	0
T109	35507	0	0	0
T110	0	12	0	0
T116	0	20	0	0
T147	0	9	0	0
T148	0	24	0	0
T153	0	8	0	0
T176	0	49	0	0
T177	0	26	0	0
T178	0	30	0	0
T179	8997	0	0	0
T180	2216	0	0	0
T181	9644	0	0	0
T182	27578	0	0	0
T183	7311	0	0	0
T184	0	10	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23316540	3420	0	0
T40	6953	0	0	0
T62	18288	0	0	0
T79	128795	0	0	0
T105	16580	26	0	0
T109	35507	0	0	0
T110	0	29	0	0
T116	0	13	0	0
T147	0	8	0	0
T148	0	18	0	0
T153	0	8	0	0
T176	0	41	0	0
T177	0	28	0	0
T178	0	24	0	0
T179	8997	0	0	0
T180	2216	0	0	0
T181	9644	0	0	0
T182	27578	0	0	0
T183	7311	0	0	0
T184	0	4	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23316540	3323	0	0
T40	6953	0	0	0
T62	18288	0	0	0
T79	128795	0	0	0
T105	16580	14	0	0
T109	35507	0	0	0
T110	0	25	0	0
T116	0	24	0	0
T147	0	10	0	0
T148	0	13	0	0
T152	0	80	0	0
T176	0	55	0	0
T177	0	14	0	0
T178	0	18	0	0
T179	8997	0	0	0
T180	2216	0	0	0
T181	9644	0	0	0
T182	27578	0	0	0
T183	7311	0	0	0
T184	0	11	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23316540	3424	0	0
T40	6953	0	0	0
T62	18288	0	0	0
T79	128795	0	0	0
T105	16580	20	0	0
T109	35507	0	0	0
T110	0	33	0	0
T116	0	4	0	0
T147	0	3	0	0
T148	0	26	0	0
T152	0	40	0	0
T153	0	20	0	0
T176	0	66	0	0
T177	0	27	0	0
T178	0	7	0	0
T179	8997	0	0	0
T180	2216	0	0	0
T181	9644	0	0	0
T182	27578	0	0	0
T183	7311	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23316540	3312	0	0
T40	6953	0	0	0
T62	18288	0	0	0
T79	128795	0	0	0
T105	16580	40	0	0
T109	35507	0	0	0
T110	0	13	0	0
T116	0	28	0	0
T147	0	1	0	0
T148	0	23	0	0
T153	0	6	0	0
T176	0	61	0	0
T177	0	22	0	0
T178	0	9	0	0
T179	8997	0	0	0
T180	2216	0	0	0
T181	9644	0	0	0
T182	27578	0	0	0
T183	7311	0	0	0
T184	0	2	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23316540	3400	0	0
T40	6953	0	0	0
T62	18288	0	0	0
T79	128795	0	0	0
T105	16580	28	0	0
T109	35507	0	0	0
T110	0	21	0	0
T116	0	30	0	0
T147	0	4	0	0
T148	0	5	0	0
T153	0	8	0	0
T176	0	42	0	0
T177	0	13	0	0
T178	0	14	0	0
T179	8997	0	0	0
T180	2216	0	0	0
T181	9644	0	0	0
T182	27578	0	0	0
T183	7311	0	0	0
T184	0	4	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23316540	3381	0	0
T40	6953	0	0	0
T62	18288	0	0	0
T79	128795	0	0	0
T105	16580	24	0	0
T109	35507	0	0	0
T110	0	32	0	0
T116	0	24	0	0
T147	0	17	0	0
T148	0	11	0	0
T153	0	6	0	0
T176	0	47	0	0
T177	0	38	0	0
T178	0	17	0	0
T179	8997	0	0	0
T180	2216	0	0	0
T181	9644	0	0	0
T182	27578	0	0	0
T183	7311	0	0	0
T184	0	7	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23316540	3318	0	0
T40	6953	0	0	0
T62	18288	0	0	0
T79	128795	0	0	0
T105	16580	9	0	0
T109	35507	0	0	0
T110	0	20	0	0
T116	0	17	0	0
T147	0	3	0	0
T148	0	7	0	0
T152	0	88	0	0
T153	0	17	0	0
T176	0	64	0	0
T177	0	51	0	0
T178	0	9	0	0
T179	8997	0	0	0
T180	2216	0	0	0
T181	9644	0	0	0
T182	27578	0	0	0
T183	7311	0	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23316540	3289	0	0
T40	6953	0	0	0
T62	18288	0	0	0
T79	128795	0	0	0
T105	16580	34	0	0
T109	35507	0	0	0
T110	0	8	0	0
T116	0	14	0	0
T147	0	12	0	0
T148	0	16	0	0
T153	0	9	0	0
T176	0	43	0	0
T177	0	48	0	0
T178	0	6	0	0
T179	8997	0	0	0
T180	2216	0	0	0
T181	9644	0	0	0
T182	27578	0	0	0
T183	7311	0	0	0
T184	0	7	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23316540	3410	0	0
T40	6953	0	0	0
T62	18288	0	0	0
T79	128795	0	0	0
T105	16580	31	0	0
T109	35507	0	0	0
T110	0	16	0	0
T116	0	14	0	0
T147	0	9	0	0
T148	0	8	0	0
T152	0	78	0	0
T153	0	10	0	0
T176	0	47	0	0
T177	0	32	0	0
T178	0	28	0	0
T179	8997	0	0	0
T180	2216	0	0	0
T181	9644	0	0	0
T182	27578	0	0	0
T183	7311	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23316540	3300	0	0
T40	6953	0	0	0
T62	18288	0	0	0
T79	128795	0	0	0
T105	16580	20	0	0
T109	35507	0	0	0
T110	0	16	0	0
T116	0	20	0	0
T147	0	10	0	0
T148	0	32	0	0
T152	0	80	0	0
T153	0	4	0	0
T176	0	47	0	0
T177	0	25	0	0
T178	0	15	0	0
T179	8997	0	0	0
T180	2216	0	0	0
T181	9644	0	0	0
T182	27578	0	0	0
T183	7311	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23316540	3147	0	0
T40	6953	0	0	0
T62	18288	0	0	0
T79	128795	0	0	0
T105	16580	26	0	0
T109	35507	0	0	0
T110	0	21	0	0
T116	0	18	0	0
T147	0	5	0	0
T148	0	14	0	0
T153	0	1	0	0
T176	0	66	0	0
T177	0	30	0	0
T178	0	8	0	0
T179	8997	0	0	0
T180	2216	0	0	0
T181	9644	0	0	0
T182	27578	0	0	0
T183	7311	0	0	0
T184	0	6	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23316540	3333	0	0
T40	6953	0	0	0
T62	18288	0	0	0
T79	128795	0	0	0
T105	16580	42	0	0
T109	35507	0	0	0
T110	0	29	0	0
T116	0	20	0	0
T147	0	8	0	0
T148	0	15	0	0
T153	0	7	0	0
T176	0	32	0	0
T177	0	24	0	0
T178	0	20	0	0
T179	8997	0	0	0
T180	2216	0	0	0
T181	9644	0	0	0
T182	27578	0	0	0
T183	7311	0	0	0
T184	0	9	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23316540	3335	0	0
T40	6953	0	0	0
T62	18288	0	0	0
T79	128795	0	0	0
T105	16580	31	0	0
T109	35507	0	0	0
T110	0	18	0	0
T116	0	34	0	0
T147	0	11	0	0
T148	0	14	0	0
T153	0	10	0	0
T176	0	64	0	0
T177	0	29	0	0
T178	0	8	0	0
T179	8997	0	0	0
T180	2216	0	0	0
T181	9644	0	0	0
T182	27578	0	0	0
T183	7311	0	0	0
T198	0	1	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23316540	3343	0	0
T40	6953	0	0	0
T62	18288	0	0	0
T79	128795	0	0	0
T105	16580	35	0	0
T109	35507	0	0	0
T110	0	13	0	0
T116	0	16	0	0
T147	0	4	0	0
T148	0	10	0	0
T153	0	10	0	0
T176	0	52	0	0
T177	0	28	0	0
T178	0	18	0	0
T179	8997	0	0	0
T180	2216	0	0	0
T181	9644	0	0	0
T182	27578	0	0	0
T183	7311	0	0	0
T184	0	1	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23316540	3326	0	0
T40	6953	0	0	0
T62	18288	0	0	0
T79	128795	0	0	0
T105	16580	29	0	0
T109	35507	0	0	0
T110	0	18	0	0
T116	0	28	0	0
T147	0	5	0	0
T148	0	15	0	0
T153	0	9	0	0
T176	0	81	0	0
T177	0	36	0	0
T178	0	21	0	0
T179	8997	0	0	0
T180	2216	0	0	0
T181	9644	0	0	0
T182	27578	0	0	0
T183	7311	0	0	0
T184	0	3	0	0