Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2582746	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

598623

1

T1

215

T2

419

T3

373

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2770780	1			T1	32611		T2	1001		T3	843
values[0x0]	204099	1			T1	52		T2	152		T3	144
values[0x1]	206490	1			T1	62		T2	166		T3	154

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1778323	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1403046

1

T1

11015

T2

692

T3

571

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26229	1			T1	134		T2	4		T3	1
valid_sources[0x01]	10230	1			T1	142		T2	2		T3	1
valid_sources[0x02]	10665	1			T1	120		T2	6		T3	10
valid_sources[0x03]	9582	1			T1	152		T2	10		T3	4
valid_sources[0x04]	10076	1			T1	107		T2	2		T3	5
valid_sources[0x05]	9718	1			T1	132		T2	8		T3	7
valid_sources[0x06]	13768	1			T1	125		T2	9		T3	5
valid_sources[0x07]	10211	1			T1	135		T2	4		T3	2
valid_sources[0x08]	10241	1			T1	130		T2	1		T3	7
valid_sources[0x09]	9650	1			T1	116		T2	3		T3	4
valid_sources[0x0a]	15995	1			T1	122		T2	4		T3	6
valid_sources[0x0b]	9430	1			T1	142		T2	7		T3	4
valid_sources[0x0c]	10457	1			T1	140		T2	3		T3	5
valid_sources[0x0d]	10690	1			T1	150		T2	6		T3	2
valid_sources[0x0e]	10721	1			T1	140		T2	3		T3	2
valid_sources[0x0f]	11467	1			T1	119		T3	1		T13	8
valid_sources[0x10]	12722	1			T1	121		T2	5		T3	7
valid_sources[0x11]	9621	1			T1	137		T2	6		T3	2
valid_sources[0x12]	9807	1			T1	105		T2	5		T3	5
valid_sources[0x13]	22838	1			T1	112		T2	1		T3	5
valid_sources[0x14]	15131	1			T1	164		T3	3		T13	13
valid_sources[0x15]	10468	1			T1	141		T2	6		T3	8
valid_sources[0x16]	12885	1			T1	126		T2	9		T3	4
valid_sources[0x17]	10669	1			T1	126		T2	8		T3	1
valid_sources[0x18]	11992	1			T1	132		T2	9		T3	4
valid_sources[0x19]	9798	1			T1	130		T2	7		T3	4
valid_sources[0x1a]	12274	1			T1	131		T2	1		T3	3
valid_sources[0x1b]	14373	1			T1	129		T2	2		T3	2
valid_sources[0x1c]	10992	1			T1	135		T2	2		T3	10
valid_sources[0x1d]	14511	1			T1	153		T2	1		T3	9
valid_sources[0x1e]	10538	1			T1	142		T2	1		T3	4
valid_sources[0x1f]	10698	1			T1	119		T2	3		T3	2
valid_sources[0x20]	19273	1			T1	122		T2	4		T3	6
valid_sources[0x21]	9618	1			T1	140		T2	3		T3	4
valid_sources[0x22]	10334	1			T1	125		T2	2		T3	5
valid_sources[0x23]	10575	1			T1	113		T2	4		T3	5
valid_sources[0x24]	12433	1			T1	126		T2	6		T3	4
valid_sources[0x25]	10715	1			T1	148		T2	4		T3	2
valid_sources[0x26]	33056	1			T1	104		T2	3		T3	3
valid_sources[0x27]	11591	1			T1	126		T2	1		T3	3
valid_sources[0x28]	16612	1			T1	159		T2	10		T3	1
valid_sources[0x29]	11866	1			T1	121		T2	7		T3	5
valid_sources[0x2a]	10947	1			T1	125		T2	3		T3	7
valid_sources[0x2b]	11936	1			T1	94		T2	6		T3	4
valid_sources[0x2c]	16515	1			T1	124		T2	9		T3	2
valid_sources[0x2d]	10885	1			T1	117		T3	3		T13	5
valid_sources[0x2e]	11011	1			T1	132		T2	5		T3	4
valid_sources[0x2f]	11253	1			T1	139		T2	10		T3	3
valid_sources[0x30]	10438	1			T1	132		T2	5		T3	4
valid_sources[0x31]	9239	1			T1	123		T2	5		T13	6
valid_sources[0x32]	10463	1			T1	126		T2	3		T3	3
valid_sources[0x33]	10160	1			T1	145		T2	8		T3	9
valid_sources[0x34]	12450	1			T1	125		T2	6		T3	9
valid_sources[0x35]	11030	1			T1	132		T2	6		T3	4
valid_sources[0x36]	9683	1			T1	142		T2	5		T3	7
valid_sources[0x37]	9713	1			T1	130		T2	5		T3	2
valid_sources[0x38]	10039	1			T1	140		T2	3		T3	2
valid_sources[0x39]	9852	1			T1	120		T2	7		T3	9
valid_sources[0x3a]	11818	1			T1	139		T2	2		T3	4
valid_sources[0x3b]	16279	1			T1	143		T2	2		T3	5
valid_sources[0x3c]	10311	1			T1	105		T2	7		T3	4
valid_sources[0x3d]	11077	1			T1	129		T2	3		T3	5
valid_sources[0x3e]	10632	1			T1	158		T2	8		T3	4
valid_sources[0x3f]	12795	1			T1	128		T2	5		T3	7
valid_sources[0x40]	9763	1			T1	96		T2	16		T3	4
valid_sources[0x41]	11639	1			T1	143		T3	5		T13	9
valid_sources[0x42]	11289	1			T1	117		T2	7		T3	5
valid_sources[0x43]	11348	1			T1	132		T2	6		T3	4
valid_sources[0x44]	11285	1			T1	111		T2	4		T3	3
valid_sources[0x45]	12338	1			T1	122		T2	4		T3	6
valid_sources[0x46]	10171	1			T1	114		T2	6		T3	2
valid_sources[0x47]	10448	1			T1	138		T2	4		T3	3
valid_sources[0x48]	10199	1			T1	149		T2	3		T3	5
valid_sources[0x49]	10806	1			T1	165		T2	4		T3	3
valid_sources[0x4a]	10717	1			T1	141		T2	8		T3	5
valid_sources[0x4b]	10036	1			T1	138		T2	11		T3	3
valid_sources[0x4c]	10087	1			T1	94		T2	8		T3	5
valid_sources[0x4d]	10520	1			T1	128		T2	1		T3	2
valid_sources[0x4e]	9592	1			T1	119		T2	6		T3	4
valid_sources[0x4f]	11399	1			T1	153		T2	9		T3	4
valid_sources[0x50]	10141	1			T1	125		T2	5		T3	1
valid_sources[0x51]	12021	1			T1	128		T2	3		T3	7
valid_sources[0x52]	9703	1			T1	120		T2	15		T3	6
valid_sources[0x53]	15481	1			T1	114		T2	9		T3	6
valid_sources[0x54]	12485	1			T1	135		T2	10		T3	3
valid_sources[0x55]	12012	1			T1	135		T2	2		T3	6
valid_sources[0x56]	10090	1			T1	147		T2	13		T3	5
valid_sources[0x57]	12094	1			T1	102		T2	4		T3	6
valid_sources[0x58]	9823	1			T1	114		T2	5		T3	6
valid_sources[0x59]	9088	1			T1	115		T2	2		T3	3
valid_sources[0x5a]	10721	1			T1	123		T2	6		T3	7
valid_sources[0x5b]	14206	1			T1	142		T2	5		T3	3
valid_sources[0x5c]	9195	1			T1	138		T2	12		T3	5
valid_sources[0x5d]	11355	1			T1	133		T2	6		T3	4
valid_sources[0x5e]	10000	1			T1	134		T2	6		T3	10
valid_sources[0x5f]	11095	1			T1	133		T2	9		T3	1
valid_sources[0x60]	12104	1			T1	139		T2	1		T3	6
valid_sources[0x61]	11122	1			T1	154		T2	2		T3	11
valid_sources[0x62]	10053	1			T1	150		T2	4		T3	1
valid_sources[0x63]	9670	1			T1	132		T2	5		T3	4
valid_sources[0x64]	9977	1			T1	110		T2	2		T3	6
valid_sources[0x65]	9635	1			T1	121		T2	5		T3	5
valid_sources[0x66]	20738	1			T1	159		T2	3		T3	4
valid_sources[0x67]	10513	1			T1	125		T2	1		T3	8
valid_sources[0x68]	9879	1			T1	134		T3	2		T13	9
valid_sources[0x69]	16786	1			T1	127		T2	6		T3	7
valid_sources[0x6a]	9206	1			T1	116		T2	8		T3	1
valid_sources[0x6b]	11024	1			T1	129		T2	12		T3	3
valid_sources[0x6c]	9544	1			T1	134		T2	6		T3	5
valid_sources[0x6d]	9839	1			T1	130		T2	2		T13	10
valid_sources[0x6e]	9867	1			T1	122		T2	3		T3	4
valid_sources[0x6f]	10807	1			T1	132		T2	3		T3	2
valid_sources[0x70]	10785	1			T1	119		T2	9		T3	2
valid_sources[0x71]	10328	1			T1	121		T2	1		T3	1
valid_sources[0x72]	9336	1			T1	104		T2	2		T3	4
valid_sources[0x73]	10108	1			T1	131		T2	9		T3	2
valid_sources[0x74]	9586	1			T1	118		T3	3		T13	11
valid_sources[0x75]	10188	1			T1	111		T2	5		T3	5
valid_sources[0x76]	9918	1			T1	146		T2	9		T3	3
valid_sources[0x77]	9575	1			T1	135		T2	6		T3	2
valid_sources[0x78]	10107	1			T1	115		T2	14		T3	5
valid_sources[0x79]	10299	1			T1	129		T2	7		T3	7
valid_sources[0x7a]	10686	1			T1	124		T2	4		T3	3
valid_sources[0x7b]	13727	1			T1	147		T3	3		T13	8
valid_sources[0x7c]	10301	1			T1	123		T2	4		T3	1
valid_sources[0x7d]	18379	1			T1	153		T2	3		T3	6
valid_sources[0x7e]	9823	1			T1	116		T2	4		T3	10
valid_sources[0x7f]	42559	1			T1	123		T2	4		T3	3
valid_sources[0x80]	10569	1			T1	128		T2	4		T3	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

319599

1

T1

181

T2

215

T3

206

values[0x0]

all_enables

biggest_size

146819

1

T1

22

T2

107

T3

87

values[0x1]

all_enables

biggest_size

132205

1

T1

12

T2

97

T3

80