Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	22380140	15007	0	0
attest_sw_binding_0_rd_A	22380140	3236	0	0
attest_sw_binding_1_rd_A	22380140	3133	0	0
attest_sw_binding_2_rd_A	22380140	3174	0	0
attest_sw_binding_3_rd_A	22380140	3118	0	0
attest_sw_binding_4_rd_A	22380140	2991	0	0
attest_sw_binding_5_rd_A	22380140	3149	0	0
attest_sw_binding_6_rd_A	22380140	3144	0	0
attest_sw_binding_7_rd_A	22380140	3154	0	0
intr_enable_rd_A	22380140	3454	0	0
key_version_rd_A	22380140	3249	0	0
max_creator_key_ver_regwen_rd_A	22380140	3025	0	0
max_owner_int_key_ver_regwen_rd_A	22380140	3053	0	0
max_owner_key_ver_regwen_rd_A	22380140	3087	0	0
reseed_interval_regwen_rd_A	22380140	3143	0	0
salt_0_rd_A	22380140	3013	0	0
salt_1_rd_A	22380140	3241	0	0
salt_2_rd_A	22380140	3129	0	0
salt_3_rd_A	22380140	3047	0	0
salt_4_rd_A	22380140	3306	0	0
salt_5_rd_A	22380140	3117	0	0
salt_6_rd_A	22380140	3000	0	0
salt_7_rd_A	22380140	2952	0	0
sealing_sw_binding_0_rd_A	22380140	2806	0	0
sealing_sw_binding_1_rd_A	22380140	3061	0	0
sealing_sw_binding_2_rd_A	22380140	3019	0	0
sealing_sw_binding_3_rd_A	22380140	3131	0	0
sealing_sw_binding_4_rd_A	22380140	3261	0	0
sealing_sw_binding_5_rd_A	22380140	3201	0	0
sealing_sw_binding_6_rd_A	22380140	3111	0	0
sealing_sw_binding_7_rd_A	22380140	3132	0	0
sideload_clear_rd_A	22380140	3119	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22380140	15007	0	0
T5	46826	743	0	0
T18	3785	0	0	0
T35	5676	0	0	0
T49	11017	0	0	0
T51	0	588	0	0
T52	2813	0	0	0
T58	0	309	0	0
T67	0	496	0	0
T70	0	72	0	0
T72	0	264	0	0
T78	8210	0	0	0
T79	16784	0	0	0
T80	91805	0	0	0
T81	160371	0	0	0
T82	11113	0	0	0
T123	0	133	0	0
T125	0	105	0	0
T126	0	56	0	0
T127	0	164	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22380140	3236	0	0
T64	15131	0	0	0
T68	5900	0	0	0
T70	49541	27	0	0
T89	3422	0	0	0
T125	0	28	0	0
T126	0	20	0	0
T127	0	24	0	0
T174	0	15	0	0
T175	0	44	0	0
T176	0	80	0	0
T177	0	27	0	0
T178	0	39	0	0
T179	0	77	0	0
T180	10008	0	0	0
T181	11881	0	0	0
T182	13012	0	0	0
T183	22371	0	0	0
T184	4733	0	0	0
T185	18756	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22380140	3133	0	0
T20	10907	0	0	0
T39	9401	9	0	0
T51	22208	0	0	0
T70	0	26	0	0
T125	0	9	0	0
T126	0	20	0	0
T127	0	73	0	0
T129	12650	0	0	0
T130	20289	0	0	0
T174	0	30	0	0
T175	0	43	0	0
T176	0	49	0	0
T177	0	18	0	0
T178	0	12	0	0
T186	37770	0	0	0
T187	8273	0	0	0
T188	3114	0	0	0
T189	15423	0	0	0
T190	11555	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22380140	3174	0	0
T64	15131	0	0	0
T68	5900	0	0	0
T70	49541	21	0	0
T89	3422	0	0	0
T125	0	23	0	0
T126	0	32	0	0
T127	0	63	0	0
T174	0	25	0	0
T175	0	65	0	0
T176	0	72	0	0
T177	0	28	0	0
T178	0	31	0	0
T179	0	78	0	0
T180	10008	0	0	0
T181	11881	0	0	0
T182	13012	0	0	0
T183	22371	0	0	0
T184	4733	0	0	0
T185	18756	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22380140	3118	0	0
T64	15131	0	0	0
T68	5900	0	0	0
T70	49541	45	0	0
T89	3422	0	0	0
T125	0	45	0	0
T126	0	13	0	0
T127	0	54	0	0
T174	0	18	0	0
T175	0	69	0	0
T176	0	58	0	0
T177	0	26	0	0
T178	0	40	0	0
T179	0	59	0	0
T180	10008	0	0	0
T181	11881	0	0	0
T182	13012	0	0	0
T183	22371	0	0	0
T184	4733	0	0	0
T185	18756	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22380140	2991	0	0
T64	15131	0	0	0
T68	5900	0	0	0
T70	49541	16	0	0
T89	3422	0	0	0
T125	0	25	0	0
T126	0	11	0	0
T127	0	43	0	0
T174	0	11	0	0
T175	0	53	0	0
T176	0	53	0	0
T177	0	40	0	0
T178	0	26	0	0
T179	0	45	0	0
T180	10008	0	0	0
T181	11881	0	0	0
T182	13012	0	0	0
T183	22371	0	0	0
T184	4733	0	0	0
T185	18756	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22380140	3149	0	0
T64	15131	0	0	0
T68	5900	0	0	0
T70	49541	26	0	0
T89	3422	0	0	0
T125	0	36	0	0
T126	0	10	0	0
T127	0	64	0	0
T174	0	22	0	0
T175	0	64	0	0
T176	0	48	0	0
T177	0	28	0	0
T178	0	21	0	0
T179	0	75	0	0
T180	10008	0	0	0
T181	11881	0	0	0
T182	13012	0	0	0
T183	22371	0	0	0
T184	4733	0	0	0
T185	18756	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22380140	3144	0	0
T64	15131	0	0	0
T68	5900	0	0	0
T70	49541	39	0	0
T89	3422	0	0	0
T125	0	14	0	0
T126	0	46	0	0
T127	0	49	0	0
T174	0	22	0	0
T175	0	62	0	0
T176	0	65	0	0
T177	0	11	0	0
T178	0	25	0	0
T179	0	78	0	0
T180	10008	0	0	0
T181	11881	0	0	0
T182	13012	0	0	0
T183	22371	0	0	0
T184	4733	0	0	0
T185	18756	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22380140	3154	0	0
T64	15131	0	0	0
T68	5900	0	0	0
T70	49541	38	0	0
T89	3422	0	0	0
T125	0	39	0	0
T126	0	9	0	0
T127	0	47	0	0
T174	0	39	0	0
T175	0	38	0	0
T176	0	81	0	0
T177	0	8	0	0
T178	0	32	0	0
T179	0	80	0	0
T180	10008	0	0	0
T181	11881	0	0	0
T182	13012	0	0	0
T183	22371	0	0	0
T184	4733	0	0	0
T185	18756	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22380140	3454	0	0
T64	15131	0	0	0
T68	5900	0	0	0
T70	49541	19	0	0
T77	0	34	0	0
T89	3422	0	0	0
T125	0	49	0	0
T126	0	13	0	0
T127	0	47	0	0
T174	0	20	0	0
T180	10008	0	0	0
T181	11881	0	0	0
T182	13012	0	0	0
T183	22371	0	0	0
T184	4733	0	0	0
T185	18756	0	0	0
T191	0	1	0	0
T192	0	21	0	0
T193	0	19	0	0
T194	0	22	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22380140	3249	0	0
T64	15131	0	0	0
T68	5900	0	0	0
T70	49541	54	0	0
T89	3422	0	0	0
T125	0	52	0	0
T126	0	26	0	0
T127	0	42	0	0
T174	0	42	0	0
T175	0	79	0	0
T176	0	67	0	0
T177	0	15	0	0
T178	0	22	0	0
T179	0	55	0	0
T180	10008	0	0	0
T181	11881	0	0	0
T182	13012	0	0	0
T183	22371	0	0	0
T184	4733	0	0	0
T185	18756	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22380140	3025	0	0
T64	15131	0	0	0
T68	5900	0	0	0
T70	49541	22	0	0
T89	3422	0	0	0
T125	0	28	0	0
T126	0	34	0	0
T127	0	64	0	0
T174	0	17	0	0
T175	0	48	0	0
T176	0	61	0	0
T177	0	22	0	0
T178	0	28	0	0
T179	0	41	0	0
T180	10008	0	0	0
T181	11881	0	0	0
T182	13012	0	0	0
T183	22371	0	0	0
T184	4733	0	0	0
T185	18756	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22380140	3053	0	0
T64	15131	0	0	0
T68	5900	0	0	0
T70	49541	33	0	0
T89	3422	0	0	0
T125	0	50	0	0
T126	0	11	0	0
T127	0	64	0	0
T174	0	26	0	0
T175	0	57	0	0
T176	0	56	0	0
T177	0	13	0	0
T178	0	15	0	0
T179	0	56	0	0
T180	10008	0	0	0
T181	11881	0	0	0
T182	13012	0	0	0
T183	22371	0	0	0
T184	4733	0	0	0
T185	18756	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22380140	3087	0	0
T64	15131	0	0	0
T68	5900	0	0	0
T70	49541	61	0	0
T89	3422	0	0	0
T125	0	38	0	0
T126	0	33	0	0
T127	0	67	0	0
T174	0	27	0	0
T175	0	50	0	0
T176	0	48	0	0
T177	0	35	0	0
T178	0	22	0	0
T179	0	67	0	0
T180	10008	0	0	0
T181	11881	0	0	0
T182	13012	0	0	0
T183	22371	0	0	0
T184	4733	0	0	0
T185	18756	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22380140	3143	0	0
T64	15131	0	0	0
T68	5900	0	0	0
T70	49541	43	0	0
T89	3422	0	0	0
T125	0	21	0	0
T126	0	42	0	0
T127	0	72	0	0
T174	0	13	0	0
T175	0	69	0	0
T176	0	97	0	0
T177	0	15	0	0
T178	0	25	0	0
T179	0	77	0	0
T180	10008	0	0	0
T181	11881	0	0	0
T182	13012	0	0	0
T183	22371	0	0	0
T184	4733	0	0	0
T185	18756	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22380140	3013	0	0
T64	15131	0	0	0
T68	5900	0	0	0
T70	49541	7	0	0
T89	3422	0	0	0
T125	0	35	0	0
T126	0	39	0	0
T127	0	54	0	0
T174	0	30	0	0
T175	0	51	0	0
T176	0	50	0	0
T177	0	16	0	0
T178	0	21	0	0
T179	0	46	0	0
T180	10008	0	0	0
T181	11881	0	0	0
T182	13012	0	0	0
T183	22371	0	0	0
T184	4733	0	0	0
T185	18756	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22380140	3241	0	0
T64	15131	0	0	0
T68	5900	0	0	0
T70	49541	31	0	0
T89	3422	0	0	0
T125	0	20	0	0
T126	0	28	0	0
T127	0	54	0	0
T174	0	33	0	0
T175	0	69	0	0
T176	0	73	0	0
T177	0	15	0	0
T178	0	25	0	0
T179	0	75	0	0
T180	10008	0	0	0
T181	11881	0	0	0
T182	13012	0	0	0
T183	22371	0	0	0
T184	4733	0	0	0
T185	18756	0	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22380140	3129	0	0
T64	15131	0	0	0
T68	5900	0	0	0
T70	49541	10	0	0
T89	3422	0	0	0
T125	0	29	0	0
T126	0	19	0	0
T127	0	49	0	0
T174	0	14	0	0
T175	0	53	0	0
T176	0	71	0	0
T177	0	6	0	0
T178	0	36	0	0
T180	10008	0	0	0
T181	11881	0	0	0
T182	13012	0	0	0
T183	22371	0	0	0
T184	4733	0	0	0
T185	18756	0	0	0
T195	0	1	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22380140	3047	0	0
T64	15131	0	0	0
T68	5900	0	0	0
T70	49541	35	0	0
T89	3422	0	0	0
T125	0	23	0	0
T126	0	12	0	0
T127	0	59	0	0
T174	0	21	0	0
T175	0	58	0	0
T176	0	84	0	0
T177	0	9	0	0
T178	0	21	0	0
T179	0	76	0	0
T180	10008	0	0	0
T181	11881	0	0	0
T182	13012	0	0	0
T183	22371	0	0	0
T184	4733	0	0	0
T185	18756	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22380140	3306	0	0
T64	15131	0	0	0
T68	5900	0	0	0
T70	49541	32	0	0
T89	3422	0	0	0
T125	0	31	0	0
T126	0	21	0	0
T127	0	56	0	0
T174	0	25	0	0
T175	0	68	0	0
T176	0	74	0	0
T177	0	14	0	0
T178	0	22	0	0
T180	10008	0	0	0
T181	11881	0	0	0
T182	13012	0	0	0
T183	22371	0	0	0
T184	4733	0	0	0
T185	18756	0	0	0
T196	0	7	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22380140	3117	0	0
T64	15131	0	0	0
T68	5900	0	0	0
T70	49541	47	0	0
T89	3422	0	0	0
T125	0	38	0	0
T126	0	27	0	0
T127	0	70	0	0
T174	0	16	0	0
T175	0	61	0	0
T176	0	89	0	0
T177	0	14	0	0
T178	0	37	0	0
T179	0	59	0	0
T180	10008	0	0	0
T181	11881	0	0	0
T182	13012	0	0	0
T183	22371	0	0	0
T184	4733	0	0	0
T185	18756	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22380140	3000	0	0
T64	15131	0	0	0
T68	5900	0	0	0
T70	49541	31	0	0
T89	3422	0	0	0
T125	0	14	0	0
T126	0	3	0	0
T127	0	39	0	0
T174	0	28	0	0
T175	0	48	0	0
T176	0	79	0	0
T177	0	11	0	0
T178	0	24	0	0
T179	0	59	0	0
T180	10008	0	0	0
T181	11881	0	0	0
T182	13012	0	0	0
T183	22371	0	0	0
T184	4733	0	0	0
T185	18756	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22380140	2952	0	0
T64	15131	0	0	0
T68	5900	0	0	0
T70	49541	29	0	0
T89	3422	0	0	0
T125	0	34	0	0
T126	0	33	0	0
T127	0	49	0	0
T174	0	29	0	0
T175	0	41	0	0
T176	0	68	0	0
T177	0	23	0	0
T178	0	34	0	0
T179	0	38	0	0
T180	10008	0	0	0
T181	11881	0	0	0
T182	13012	0	0	0
T183	22371	0	0	0
T184	4733	0	0	0
T185	18756	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22380140	2806	0	0
T64	15131	0	0	0
T68	5900	0	0	0
T70	49541	13	0	0
T89	3422	0	0	0
T125	0	15	0	0
T126	0	15	0	0
T127	0	50	0	0
T174	0	40	0	0
T175	0	41	0	0
T176	0	85	0	0
T177	0	19	0	0
T178	0	16	0	0
T179	0	46	0	0
T180	10008	0	0	0
T181	11881	0	0	0
T182	13012	0	0	0
T183	22371	0	0	0
T184	4733	0	0	0
T185	18756	0	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22380140	3061	0	0
T64	15131	0	0	0
T68	5900	0	0	0
T70	49541	27	0	0
T89	3422	0	0	0
T125	0	36	0	0
T126	0	20	0	0
T127	0	32	0	0
T174	0	59	0	0
T175	0	65	0	0
T176	0	66	0	0
T177	0	3	0	0
T178	0	37	0	0
T179	0	44	0	0
T180	10008	0	0	0
T181	11881	0	0	0
T182	13012	0	0	0
T183	22371	0	0	0
T184	4733	0	0	0
T185	18756	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22380140	3019	0	0
T64	15131	0	0	0
T68	5900	0	0	0
T70	49541	27	0	0
T89	3422	0	0	0
T125	0	25	0	0
T126	0	7	0	0
T127	0	35	0	0
T174	0	35	0	0
T175	0	50	0	0
T176	0	70	0	0
T177	0	10	0	0
T178	0	19	0	0
T179	0	42	0	0
T180	10008	0	0	0
T181	11881	0	0	0
T182	13012	0	0	0
T183	22371	0	0	0
T184	4733	0	0	0
T185	18756	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22380140	3131	0	0
T64	15131	0	0	0
T68	5900	0	0	0
T70	49541	16	0	0
T89	3422	0	0	0
T125	0	27	0	0
T126	0	38	0	0
T127	0	57	0	0
T174	0	32	0	0
T175	0	62	0	0
T176	0	78	0	0
T177	0	22	0	0
T178	0	34	0	0
T179	0	79	0	0
T180	10008	0	0	0
T181	11881	0	0	0
T182	13012	0	0	0
T183	22371	0	0	0
T184	4733	0	0	0
T185	18756	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22380140	3261	0	0
T64	15131	0	0	0
T68	5900	0	0	0
T70	49541	21	0	0
T89	3422	0	0	0
T125	0	22	0	0
T126	0	23	0	0
T127	0	95	0	0
T174	0	23	0	0
T175	0	41	0	0
T176	0	62	0	0
T177	0	24	0	0
T178	0	22	0	0
T179	0	58	0	0
T180	10008	0	0	0
T181	11881	0	0	0
T182	13012	0	0	0
T183	22371	0	0	0
T184	4733	0	0	0
T185	18756	0	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22380140	3201	0	0
T64	15131	0	0	0
T68	5900	0	0	0
T70	49541	51	0	0
T89	3422	0	0	0
T125	0	37	0	0
T126	0	11	0	0
T127	0	47	0	0
T174	0	7	0	0
T175	0	62	0	0
T176	0	58	0	0
T177	0	17	0	0
T178	0	27	0	0
T179	0	72	0	0
T180	10008	0	0	0
T181	11881	0	0	0
T182	13012	0	0	0
T183	22371	0	0	0
T184	4733	0	0	0
T185	18756	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22380140	3111	0	0
T64	15131	0	0	0
T68	5900	0	0	0
T70	49541	48	0	0
T89	3422	0	0	0
T125	0	18	0	0
T126	0	14	0	0
T127	0	88	0	0
T174	0	27	0	0
T175	0	54	0	0
T176	0	61	0	0
T177	0	26	0	0
T178	0	27	0	0
T179	0	62	0	0
T180	10008	0	0	0
T181	11881	0	0	0
T182	13012	0	0	0
T183	22371	0	0	0
T184	4733	0	0	0
T185	18756	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22380140	3132	0	0
T64	15131	0	0	0
T68	5900	0	0	0
T70	49541	32	0	0
T89	3422	0	0	0
T125	0	24	0	0
T126	0	11	0	0
T127	0	61	0	0
T174	0	15	0	0
T175	0	45	0	0
T176	0	83	0	0
T177	0	18	0	0
T178	0	22	0	0
T179	0	75	0	0
T180	10008	0	0	0
T181	11881	0	0	0
T182	13012	0	0	0
T183	22371	0	0	0
T184	4733	0	0	0
T185	18756	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22380140	3119	0	0
T64	15131	0	0	0
T68	5900	0	0	0
T70	49541	46	0	0
T89	3422	0	0	0
T125	0	32	0	0
T126	0	19	0	0
T127	0	62	0	0
T174	0	22	0	0
T175	0	50	0	0
T176	0	55	0	0
T177	0	13	0	0
T178	0	22	0	0
T179	0	36	0	0
T180	10008	0	0	0
T181	11881	0	0	0
T182	13012	0	0	0
T183	22371	0	0	0
T184	4733	0	0	0
T185	18756	0	0	0