Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2859376	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

612789

1

T1

593

T2

155

T3

144

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3062933	1			T1	5807		T2	502		T3	843
values[0x0]	202601	1			T1	208		T2	64		T3	45
values[0x1]	206631	1			T1	210		T2	41		T3	39

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1964915	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1507250

1

T1

2451

T2

263

T3

372

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	35645	1			T1	25		T2	4		T3	4
valid_sources[0x01]	11529	1			T1	22		T2	1		T3	5
valid_sources[0x02]	10659	1			T1	21		T2	3		T3	4
valid_sources[0x03]	17198	1			T1	34		T2	4		T3	5
valid_sources[0x04]	15222	1			T1	33		T2	2		T3	2
valid_sources[0x05]	10215	1			T1	25		T2	4		T3	1
valid_sources[0x06]	10291	1			T1	16		T2	3		T3	1
valid_sources[0x07]	10246	1			T1	19		T2	2		T3	4
valid_sources[0x08]	10221	1			T1	11		T2	2		T3	5
valid_sources[0x09]	14347	1			T1	27		T3	6		T4	11
valid_sources[0x0a]	10747	1			T1	19		T2	1		T3	3
valid_sources[0x0b]	10137	1			T1	48		T3	1		T4	41
valid_sources[0x0c]	10341	1			T1	20		T2	3		T3	9
valid_sources[0x0d]	24671	1			T1	23		T2	6		T3	3
valid_sources[0x0e]	9805	1			T1	14		T2	3		T3	6
valid_sources[0x0f]	9964	1			T1	18		T2	5		T3	6
valid_sources[0x10]	11054	1			T1	24		T2	1		T5	9
valid_sources[0x11]	10685	1			T1	47		T2	1		T3	8
valid_sources[0x12]	11349	1			T1	22		T3	1		T4	20
valid_sources[0x13]	11304	1			T1	14		T2	1		T3	2
valid_sources[0x14]	14292	1			T1	19		T2	2		T3	8
valid_sources[0x15]	12788	1			T1	25		T3	4		T4	21
valid_sources[0x16]	12111	1			T1	29		T2	3		T3	7
valid_sources[0x17]	9727	1			T1	16		T2	6		T3	3
valid_sources[0x18]	12439	1			T1	11		T2	3		T3	4
valid_sources[0x19]	15626	1			T1	12		T3	1		T5	7
valid_sources[0x1a]	10331	1			T1	18		T2	3		T3	5
valid_sources[0x1b]	11570	1			T1	19		T2	4		T3	3
valid_sources[0x1c]	15890	1			T1	20		T3	6		T5	16
valid_sources[0x1d]	24488	1			T1	8		T2	4		T3	2
valid_sources[0x1e]	15927	1			T1	22		T2	2		T3	5
valid_sources[0x1f]	13833	1			T1	27		T3	2		T4	24
valid_sources[0x20]	11601	1			T1	24		T2	1		T3	2
valid_sources[0x21]	9941	1			T1	21		T2	1		T3	1
valid_sources[0x22]	10686	1			T1	31		T2	3		T3	4
valid_sources[0x23]	26066	1			T1	19		T2	4		T3	6
valid_sources[0x24]	10028	1			T1	32		T2	1		T3	3
valid_sources[0x25]	16815	1			T1	26		T2	5		T3	1
valid_sources[0x26]	10309	1			T1	20		T2	1		T3	4
valid_sources[0x27]	9673	1			T1	24		T2	3		T3	2
valid_sources[0x28]	18148	1			T1	50		T2	5		T3	4
valid_sources[0x29]	11524	1			T1	29		T2	3		T3	6
valid_sources[0x2a]	11022	1			T1	29		T2	2		T3	1
valid_sources[0x2b]	9977	1			T1	23		T2	1		T3	3
valid_sources[0x2c]	13394	1			T1	16		T2	4		T3	4
valid_sources[0x2d]	9998	1			T1	21		T2	4		T3	4
valid_sources[0x2e]	10813	1			T1	34		T2	3		T3	6
valid_sources[0x2f]	10349	1			T1	16		T2	3		T3	3
valid_sources[0x30]	11317	1			T1	21		T2	5		T3	2
valid_sources[0x31]	22781	1			T1	29		T2	1		T3	1
valid_sources[0x32]	9728	1			T1	38		T2	5		T3	5
valid_sources[0x33]	10470	1			T1	32		T2	3		T3	5
valid_sources[0x34]	10840	1			T1	39		T2	1		T3	2
valid_sources[0x35]	13407	1			T1	15		T2	2		T3	6
valid_sources[0x36]	12258	1			T1	17		T2	1		T3	2
valid_sources[0x37]	20154	1			T1	37		T2	1		T3	2
valid_sources[0x38]	10482	1			T1	36		T2	6		T3	4
valid_sources[0x39]	10337	1			T1	16		T2	3		T3	3
valid_sources[0x3a]	11932	1			T1	20		T2	4		T3	2
valid_sources[0x3b]	10989	1			T1	21		T2	1		T3	5
valid_sources[0x3c]	12133	1			T1	27		T2	2		T3	4
valid_sources[0x3d]	10527	1			T1	22		T2	1		T3	1
valid_sources[0x3e]	10566	1			T1	26		T3	2		T4	33
valid_sources[0x3f]	39635	1			T1	18		T2	1		T3	2
valid_sources[0x40]	10313	1			T1	13		T2	5		T3	4
valid_sources[0x41]	10905	1			T1	31		T2	4		T3	6
valid_sources[0x42]	14459	1			T1	37		T2	3		T3	5
valid_sources[0x43]	11047	1			T1	26		T2	3		T3	5
valid_sources[0x44]	11535	1			T1	23		T2	2		T4	22
valid_sources[0x45]	53614	1			T1	25		T2	3		T5	6
valid_sources[0x46]	10825	1			T1	13		T2	4		T3	5
valid_sources[0x47]	9965	1			T1	23		T2	2		T3	4
valid_sources[0x48]	9951	1			T1	11		T2	2		T3	3
valid_sources[0x49]	10003	1			T1	19		T2	4		T3	2
valid_sources[0x4a]	12609	1			T1	38		T2	2		T3	5
valid_sources[0x4b]	9617	1			T1	16		T2	2		T3	1
valid_sources[0x4c]	11968	1			T1	15		T2	4		T3	2
valid_sources[0x4d]	10176	1			T1	23		T2	1		T3	2
valid_sources[0x4e]	11833	1			T1	12		T2	1		T3	3
valid_sources[0x4f]	14468	1			T1	27		T2	2		T3	8
valid_sources[0x50]	10661	1			T1	29		T2	3		T3	4
valid_sources[0x51]	12598	1			T1	32		T2	1		T3	2
valid_sources[0x52]	78566	1			T1	22		T2	1		T4	4
valid_sources[0x53]	11697	1			T1	15		T2	2		T3	1
valid_sources[0x54]	29658	1			T1	19		T2	4		T3	3
valid_sources[0x55]	9761	1			T1	36		T2	7		T3	6
valid_sources[0x56]	9823	1			T1	25		T2	1		T3	1
valid_sources[0x57]	9887	1			T1	23		T2	3		T3	2
valid_sources[0x58]	12696	1			T1	19		T3	4		T5	5
valid_sources[0x59]	10677	1			T1	34		T2	2		T3	3
valid_sources[0x5a]	10620	1			T1	26		T2	5		T3	4
valid_sources[0x5b]	11957	1			T1	27		T2	7		T3	2
valid_sources[0x5c]	11769	1			T1	24		T2	3		T3	2
valid_sources[0x5d]	14076	1			T1	19		T2	2		T3	3
valid_sources[0x5e]	11359	1			T1	25		T2	1		T3	4
valid_sources[0x5f]	10587	1			T1	38		T2	5		T3	2
valid_sources[0x60]	10989	1			T1	31		T3	1		T4	18
valid_sources[0x61]	12678	1			T1	26		T2	2		T3	8
valid_sources[0x62]	12359	1			T1	24		T2	1		T3	2
valid_sources[0x63]	12383	1			T1	20		T2	1		T3	4
valid_sources[0x64]	10687	1			T1	33		T2	4		T3	2
valid_sources[0x65]	12123	1			T1	12		T2	1		T3	3
valid_sources[0x66]	11219	1			T1	54		T2	1		T3	5
valid_sources[0x67]	11500	1			T1	15		T2	1		T3	1
valid_sources[0x68]	11249	1			T1	15		T2	1		T3	6
valid_sources[0x69]	10900	1			T1	26		T2	2		T3	3
valid_sources[0x6a]	11986	1			T1	21		T2	3		T3	2
valid_sources[0x6b]	10430	1			T1	38		T2	4		T3	5
valid_sources[0x6c]	10429	1			T1	37		T2	4		T3	6
valid_sources[0x6d]	10523	1			T1	26		T2	2		T3	6
valid_sources[0x6e]	10666	1			T1	30		T2	1		T4	6
valid_sources[0x6f]	10279	1			T1	28		T3	4		T5	6
valid_sources[0x70]	10002	1			T1	32		T2	5		T3	1
valid_sources[0x71]	11816	1			T1	23		T2	4		T3	5
valid_sources[0x72]	10045	1			T1	17		T3	3		T4	7
valid_sources[0x73]	10255	1			T1	26		T2	4		T3	7
valid_sources[0x74]	11584	1			T1	36		T2	2		T3	4
valid_sources[0x75]	10137	1			T1	32		T2	2		T3	8
valid_sources[0x76]	10236	1			T1	19		T2	2		T3	5
valid_sources[0x77]	10253	1			T1	15		T3	3		T5	6
valid_sources[0x78]	13566	1			T1	25		T2	1		T3	4
valid_sources[0x79]	11802	1			T1	24		T2	1		T3	3
valid_sources[0x7a]	10819	1			T1	29		T2	1		T3	8
valid_sources[0x7b]	9786	1			T1	23		T2	1		T3	3
valid_sources[0x7c]	9859	1			T1	19		T2	1		T3	9
valid_sources[0x7d]	12041	1			T1	18		T2	1		T3	2
valid_sources[0x7e]	54436	1			T1	30		T2	2		T3	4
valid_sources[0x7f]	21093	1			T1	30		T2	6		T3	3
valid_sources[0x80]	10349	1			T1	29		T2	2		T3	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

335171

1

T1

304

T2

135

T3

120

values[0x0]

all_enables

biggest_size

145910

1

T1

151

T2

13

T3

18

values[0x1]

all_enables

biggest_size

131708

1

T1

138

T2

7

T3

6