Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3040089	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

617558

1

T1

104

T2

150

T3

775

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3237572	1			T1	5605		T2	1588		T3	814
values[0x0]	207852	1			T1	63		T2	40		T3	303
values[0x1]	212223	1			T1	49		T2	38		T3	304

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2086270	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1571377

1

T1

1957

T2

633

T3

915

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11688	1			T1	14		T2	7		T3	13
valid_sources[0x01]	19766	1			T1	19		T2	17		T3	5
valid_sources[0x02]	12505	1			T1	24		T2	5		T3	7
valid_sources[0x03]	12783	1			T1	30		T2	4		T3	2
valid_sources[0x04]	18863	1			T1	15		T2	8		T3	8
valid_sources[0x05]	12179	1			T1	14		T2	8		T3	6
valid_sources[0x06]	14224	1			T1	28		T2	2		T3	5
valid_sources[0x07]	12547	1			T1	10		T2	3		T3	15
valid_sources[0x08]	13188	1			T1	25		T2	8		T3	6
valid_sources[0x09]	13209	1			T1	33		T2	2		T3	5
valid_sources[0x0a]	12667	1			T1	22		T2	16		T3	5
valid_sources[0x0b]	12256	1			T1	35		T2	7		T3	6
valid_sources[0x0c]	13052	1			T1	9		T2	6		T3	3
valid_sources[0x0d]	12016	1			T1	27		T2	7		T3	4
valid_sources[0x0e]	12163	1			T1	16		T2	9		T3	5
valid_sources[0x0f]	12384	1			T1	16		T2	1		T3	9
valid_sources[0x10]	14876	1			T1	15		T2	5		T3	3
valid_sources[0x11]	13301	1			T1	28		T2	15		T3	6
valid_sources[0x12]	12025	1			T1	28		T2	6		T3	5
valid_sources[0x13]	15470	1			T1	24		T2	13		T3	2
valid_sources[0x14]	12946	1			T1	27		T2	7		T3	1
valid_sources[0x15]	12191	1			T1	21		T2	10		T3	10
valid_sources[0x16]	17489	1			T1	26		T2	8		T3	3
valid_sources[0x17]	12443	1			T1	26		T2	3		T3	2
valid_sources[0x18]	12128	1			T1	9		T2	8		T3	5
valid_sources[0x19]	12648	1			T1	23		T2	7		T3	2
valid_sources[0x1a]	23894	1			T1	31		T2	2		T3	8
valid_sources[0x1b]	22179	1			T1	17		T2	4		T3	2
valid_sources[0x1c]	12865	1			T1	18		T2	9		T3	5
valid_sources[0x1d]	12040	1			T1	20		T2	5		T3	3
valid_sources[0x1e]	16418	1			T1	26		T2	12		T3	11
valid_sources[0x1f]	13416	1			T1	18		T2	4		T3	3
valid_sources[0x20]	12450	1			T1	22		T2	3		T3	10
valid_sources[0x21]	11833	1			T1	19		T2	4		T3	12
valid_sources[0x22]	12311	1			T1	21		T2	7		T3	13
valid_sources[0x23]	12445	1			T1	21		T2	2		T3	3
valid_sources[0x24]	14103	1			T1	30		T2	5		T3	6
valid_sources[0x25]	11871	1			T1	35		T2	7		T3	7
valid_sources[0x26]	50714	1			T1	31		T2	9		T3	1
valid_sources[0x27]	13455	1			T1	32		T2	8		T3	2
valid_sources[0x28]	12662	1			T1	31		T2	5		T3	5
valid_sources[0x29]	14004	1			T1	21		T2	3		T3	4
valid_sources[0x2a]	11963	1			T1	25		T2	14		T3	8
valid_sources[0x2b]	13626	1			T1	17		T2	2		T3	11
valid_sources[0x2c]	13085	1			T1	27		T2	7		T3	3
valid_sources[0x2d]	12296	1			T1	22		T2	8		T3	4
valid_sources[0x2e]	12557	1			T1	19		T2	13		T3	10
valid_sources[0x2f]	13275	1			T1	12		T2	4		T3	12
valid_sources[0x30]	11289	1			T1	27		T2	3		T3	4
valid_sources[0x31]	12453	1			T1	12		T2	4		T3	6
valid_sources[0x32]	12109	1			T1	13		T2	3		T3	5
valid_sources[0x33]	12102	1			T1	31		T2	9		T3	9
valid_sources[0x34]	17643	1			T1	20		T2	6		T5	100
valid_sources[0x35]	11605	1			T1	20		T2	9		T3	3
valid_sources[0x36]	12011	1			T1	26		T2	5		T3	6
valid_sources[0x37]	53163	1			T1	18		T2	6		T3	1
valid_sources[0x38]	22146	1			T1	36		T2	5		T3	7
valid_sources[0x39]	15835	1			T1	15		T2	10		T3	4
valid_sources[0x3a]	11943	1			T1	36		T2	2		T3	8
valid_sources[0x3b]	12068	1			T1	16		T2	4		T3	4
valid_sources[0x3c]	15650	1			T1	25		T2	10		T3	3
valid_sources[0x3d]	12383	1			T1	43		T2	5		T3	12
valid_sources[0x3e]	12733	1			T1	24		T2	4		T3	12
valid_sources[0x3f]	13622	1			T1	20		T2	11		T3	9
valid_sources[0x40]	12258	1			T1	34		T2	5		T3	10
valid_sources[0x41]	12094	1			T1	26		T2	6		T3	1
valid_sources[0x42]	14520	1			T1	17		T2	4		T3	3
valid_sources[0x43]	11476	1			T1	21		T2	8		T3	4
valid_sources[0x44]	11799	1			T1	27		T2	5		T3	3
valid_sources[0x45]	12107	1			T1	31		T2	11		T3	2
valid_sources[0x46]	13318	1			T1	16		T2	5		T3	3
valid_sources[0x47]	13520	1			T1	17		T2	8		T3	1
valid_sources[0x48]	11891	1			T1	33		T2	4		T3	5
valid_sources[0x49]	11849	1			T1	23		T2	7		T3	6
valid_sources[0x4a]	17204	1			T1	18		T2	8		T3	9
valid_sources[0x4b]	12980	1			T1	35		T2	13		T3	8
valid_sources[0x4c]	12708	1			T1	12		T2	4		T3	1
valid_sources[0x4d]	13324	1			T1	23		T2	3		T5	70
valid_sources[0x4e]	13448	1			T1	20		T2	4		T3	5
valid_sources[0x4f]	19382	1			T1	24		T2	9		T3	1
valid_sources[0x50]	12266	1			T1	23		T2	9		T3	7
valid_sources[0x51]	13408	1			T1	41		T2	11		T3	7
valid_sources[0x52]	13738	1			T1	18		T2	15		T3	3
valid_sources[0x53]	15623	1			T1	25		T2	8		T3	6
valid_sources[0x54]	28167	1			T1	33		T2	11		T3	16
valid_sources[0x55]	12299	1			T1	21		T2	8		T3	11
valid_sources[0x56]	11900	1			T1	23		T2	9		T3	1
valid_sources[0x57]	12044	1			T1	26		T2	6		T3	10
valid_sources[0x58]	12207	1			T1	27		T2	13		T3	5
valid_sources[0x59]	11989	1			T1	18		T2	3		T3	4
valid_sources[0x5a]	12531	1			T1	19		T2	4		T3	6
valid_sources[0x5b]	13677	1			T1	15		T2	11		T3	1
valid_sources[0x5c]	14667	1			T1	36		T2	7		T3	4
valid_sources[0x5d]	12696	1			T1	25		T2	3		T3	6
valid_sources[0x5e]	12702	1			T1	8		T2	4		T3	4
valid_sources[0x5f]	14476	1			T1	27		T2	6		T3	7
valid_sources[0x60]	11590	1			T1	16		T2	15		T3	10
valid_sources[0x61]	12318	1			T1	27		T2	8		T3	7
valid_sources[0x62]	12286	1			T1	38		T2	7		T3	7
valid_sources[0x63]	11528	1			T1	11		T2	6		T3	4
valid_sources[0x64]	13167	1			T1	26		T2	12		T3	13
valid_sources[0x65]	13585	1			T1	15		T2	5		T3	5
valid_sources[0x66]	14461	1			T1	35		T2	6		T3	3
valid_sources[0x67]	11773	1			T1	9		T2	2		T3	5
valid_sources[0x68]	11518	1			T1	41		T2	4		T3	7
valid_sources[0x69]	27320	1			T1	30		T2	8		T3	2
valid_sources[0x6a]	14060	1			T1	30		T2	10		T3	5
valid_sources[0x6b]	11858	1			T1	21		T2	6		T3	3
valid_sources[0x6c]	12179	1			T1	22		T2	10		T3	1
valid_sources[0x6d]	14003	1			T1	19		T2	3		T3	4
valid_sources[0x6e]	12481	1			T1	2		T2	3		T3	3
valid_sources[0x6f]	13952	1			T1	23		T2	15		T3	6
valid_sources[0x70]	12951	1			T1	25		T2	9		T3	5
valid_sources[0x71]	12012	1			T1	23		T2	2		T3	1
valid_sources[0x72]	12430	1			T1	31		T2	2		T3	8
valid_sources[0x73]	22175	1			T1	32		T2	6		T3	2
valid_sources[0x74]	14599	1			T1	23		T2	4		T3	8
valid_sources[0x75]	14591	1			T1	25		T2	8		T3	4
valid_sources[0x76]	12027	1			T1	24		T2	17		T3	1
valid_sources[0x77]	12763	1			T1	27		T2	7		T3	8
valid_sources[0x78]	21089	1			T1	35		T2	12		T3	5
valid_sources[0x79]	16187	1			T1	32		T2	10		T3	4
valid_sources[0x7a]	17335	1			T1	11		T2	5		T3	5
valid_sources[0x7b]	12953	1			T1	8		T2	5		T3	8
valid_sources[0x7c]	13285	1			T1	14		T2	6		T3	3
valid_sources[0x7d]	11680	1			T1	20		T2	4		T3	1
valid_sources[0x7e]	14471	1			T1	25		T2	1		T3	1
valid_sources[0x7f]	14214	1			T1	30		T2	8		T3	8
valid_sources[0x80]	12306	1			T1	40		T2	11		T3	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

333469

1

T1

46

T2

123

T3

363

values[0x0]

all_enables

biggest_size

148899

1

T1

36

T2

20

T3

224

values[0x1]

all_enables

biggest_size

135190

1

T1

22

T2

7

T3

188