Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	24819867	17758	0	0
attest_sw_binding_0_rd_A	24819867	4469	0	0
attest_sw_binding_1_rd_A	24819867	4467	0	0
attest_sw_binding_2_rd_A	24819867	4321	0	0
attest_sw_binding_3_rd_A	24819867	4528	0	0
attest_sw_binding_4_rd_A	24819867	4517	0	0
attest_sw_binding_5_rd_A	24819867	4401	0	0
attest_sw_binding_6_rd_A	24819867	4432	0	0
attest_sw_binding_7_rd_A	24819867	4442	0	0
intr_enable_rd_A	24819867	5134	0	0
key_version_rd_A	24819867	4671	0	0
max_creator_key_ver_regwen_rd_A	24819867	4649	0	0
max_owner_int_key_ver_regwen_rd_A	24819867	4346	0	0
max_owner_key_ver_regwen_rd_A	24819867	4543	0	0
reseed_interval_regwen_rd_A	24819867	4416	0	0
salt_0_rd_A	24819867	4385	0	0
salt_1_rd_A	24819867	4381	0	0
salt_2_rd_A	24819867	4543	0	0
salt_3_rd_A	24819867	4596	0	0
salt_4_rd_A	24819867	4568	0	0
salt_5_rd_A	24819867	4555	0	0
salt_6_rd_A	24819867	4493	0	0
salt_7_rd_A	24819867	4588	0	0
sealing_sw_binding_0_rd_A	24819867	4542	0	0
sealing_sw_binding_1_rd_A	24819867	4592	0	0
sealing_sw_binding_2_rd_A	24819867	4558	0	0
sealing_sw_binding_3_rd_A	24819867	4675	0	0
sealing_sw_binding_4_rd_A	24819867	4532	0	0
sealing_sw_binding_5_rd_A	24819867	4604	0	0
sealing_sw_binding_6_rd_A	24819867	4699	0	0
sealing_sw_binding_7_rd_A	24819867	4453	0	0
sideload_clear_rd_A	24819867	4635	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24819867	17758	0	0
T47	8101	0	0	0
T62	11426	0	0	0
T67	0	1046	0	0
T71	7287	0	0	0
T72	62142	0	0	0
T73	32440	0	0	0
T76	0	831	0	0
T112	17952	469	0	0
T114	0	223	0	0
T115	0	355	0	0
T128	0	309	0	0
T129	0	569	0	0
T130	0	527	0	0
T131	0	26	0	0
T132	3900	0	0	0
T133	4203	0	0	0
T134	6278	0	0	0
T135	998	0	0	0
T136	0	141	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24819867	4469	0	0
T24	57253	0	0	0
T39	4693	0	0	0
T49	44893	0	0	0
T54	5750	2	0	0
T107	3515	0	0	0
T108	61115	0	0	0
T109	3529	0	0	0
T110	7788	0	0	0
T111	3357	0	0	0
T115	0	23	0	0
T131	0	22	0	0
T139	7018	0	0	0
T181	0	29	0	0
T182	0	66	0	0
T183	0	48	0	0
T184	0	41	0	0
T185	0	36	0	0
T186	0	17	0	0
T187	0	15	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24819867	4467	0	0
T115	24244	30	0	0
T131	0	17	0	0
T181	0	29	0	0
T182	0	69	0	0
T183	0	29	0	0
T184	0	68	0	0
T185	0	42	0	0
T186	0	7	0	0
T187	0	18	0	0
T188	0	29	0	0
T189	15976	0	0	0
T190	15372	0	0	0
T191	3374	0	0	0
T192	12488	0	0	0
T193	9875	0	0	0
T194	5272	0	0	0
T195	12038	0	0	0
T196	1770	0	0	0
T197	8932	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24819867	4321	0	0
T115	24244	39	0	0
T131	0	24	0	0
T181	0	10	0	0
T182	0	47	0	0
T183	0	37	0	0
T184	0	30	0	0
T185	0	26	0	0
T186	0	20	0	0
T187	0	42	0	0
T188	0	23	0	0
T189	15976	0	0	0
T190	15372	0	0	0
T191	3374	0	0	0
T192	12488	0	0	0
T193	9875	0	0	0
T194	5272	0	0	0
T195	12038	0	0	0
T196	1770	0	0	0
T197	8932	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24819867	4528	0	0
T115	24244	30	0	0
T131	0	34	0	0
T181	0	24	0	0
T182	0	49	0	0
T183	0	29	0	0
T184	0	74	0	0
T185	0	16	0	0
T186	0	9	0	0
T187	0	29	0	0
T188	0	34	0	0
T189	15976	0	0	0
T190	15372	0	0	0
T191	3374	0	0	0
T192	12488	0	0	0
T193	9875	0	0	0
T194	5272	0	0	0
T195	12038	0	0	0
T196	1770	0	0	0
T197	8932	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24819867	4517	0	0
T115	24244	45	0	0
T131	0	40	0	0
T181	0	35	0	0
T182	0	70	0	0
T183	0	26	0	0
T184	0	54	0	0
T185	0	30	0	0
T186	0	18	0	0
T187	0	17	0	0
T188	0	14	0	0
T189	15976	0	0	0
T190	15372	0	0	0
T191	3374	0	0	0
T192	12488	0	0	0
T193	9875	0	0	0
T194	5272	0	0	0
T195	12038	0	0	0
T196	1770	0	0	0
T197	8932	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24819867	4401	0	0
T115	24244	39	0	0
T131	0	19	0	0
T181	0	26	0	0
T182	0	40	0	0
T183	0	23	0	0
T184	0	57	0	0
T185	0	19	0	0
T186	0	9	0	0
T187	0	34	0	0
T188	0	27	0	0
T189	15976	0	0	0
T190	15372	0	0	0
T191	3374	0	0	0
T192	12488	0	0	0
T193	9875	0	0	0
T194	5272	0	0	0
T195	12038	0	0	0
T196	1770	0	0	0
T197	8932	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24819867	4432	0	0
T115	24244	50	0	0
T131	0	34	0	0
T181	0	46	0	0
T182	0	40	0	0
T183	0	16	0	0
T184	0	56	0	0
T185	0	33	0	0
T186	0	19	0	0
T187	0	34	0	0
T188	0	20	0	0
T189	15976	0	0	0
T190	15372	0	0	0
T191	3374	0	0	0
T192	12488	0	0	0
T193	9875	0	0	0
T194	5272	0	0	0
T195	12038	0	0	0
T196	1770	0	0	0
T197	8932	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24819867	4442	0	0
T115	24244	21	0	0
T131	0	40	0	0
T181	0	48	0	0
T182	0	43	0	0
T183	0	34	0	0
T184	0	64	0	0
T185	0	56	0	0
T186	0	9	0	0
T187	0	15	0	0
T188	0	21	0	0
T189	15976	0	0	0
T190	15372	0	0	0
T191	3374	0	0	0
T192	12488	0	0	0
T193	9875	0	0	0
T194	5272	0	0	0
T195	12038	0	0	0
T196	1770	0	0	0
T197	8932	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24819867	5134	0	0
T6	63338	50	0	0
T55	0	1	0	0
T59	0	27	0	0
T77	0	14	0	0
T112	17952	0	0	0
T115	0	57	0	0
T131	0	34	0	0
T132	3900	0	0	0
T181	0	31	0	0
T182	0	119	0	0
T198	0	33	0	0
T199	0	28	0	0
T200	3383	0	0	0
T201	6456	0	0	0
T202	9753	0	0	0
T203	9780	0	0	0
T204	8948	0	0	0
T205	3152	0	0	0
T206	121519	0	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24819867	4671	0	0
T115	24244	18	0	0
T131	0	38	0	0
T181	0	32	0	0
T182	0	66	0	0
T183	0	12	0	0
T184	0	64	0	0
T185	0	14	0	0
T186	0	16	0	0
T187	0	20	0	0
T188	0	25	0	0
T189	15976	0	0	0
T190	15372	0	0	0
T191	3374	0	0	0
T192	12488	0	0	0
T193	9875	0	0	0
T194	5272	0	0	0
T195	12038	0	0	0
T196	1770	0	0	0
T197	8932	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24819867	4649	0	0
T115	24244	30	0	0
T131	0	31	0	0
T181	0	32	0	0
T182	0	54	0	0
T183	0	24	0	0
T184	0	55	0	0
T185	0	31	0	0
T186	0	27	0	0
T187	0	32	0	0
T188	0	20	0	0
T189	15976	0	0	0
T190	15372	0	0	0
T191	3374	0	0	0
T192	12488	0	0	0
T193	9875	0	0	0
T194	5272	0	0	0
T195	12038	0	0	0
T196	1770	0	0	0
T197	8932	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24819867	4346	0	0
T115	24244	23	0	0
T131	0	40	0	0
T181	0	40	0	0
T182	0	57	0	0
T183	0	25	0	0
T184	0	52	0	0
T185	0	24	0	0
T186	0	10	0	0
T187	0	18	0	0
T188	0	32	0	0
T189	15976	0	0	0
T190	15372	0	0	0
T191	3374	0	0	0
T192	12488	0	0	0
T193	9875	0	0	0
T194	5272	0	0	0
T195	12038	0	0	0
T196	1770	0	0	0
T197	8932	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24819867	4543	0	0
T115	24244	30	0	0
T131	0	17	0	0
T181	0	23	0	0
T182	0	105	0	0
T183	0	33	0	0
T184	0	42	0	0
T185	0	49	0	0
T186	0	6	0	0
T187	0	24	0	0
T188	0	32	0	0
T189	15976	0	0	0
T190	15372	0	0	0
T191	3374	0	0	0
T192	12488	0	0	0
T193	9875	0	0	0
T194	5272	0	0	0
T195	12038	0	0	0
T196	1770	0	0	0
T197	8932	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24819867	4416	0	0
T115	24244	34	0	0
T131	0	29	0	0
T181	0	46	0	0
T182	0	50	0	0
T183	0	32	0	0
T184	0	36	0	0
T185	0	23	0	0
T186	0	12	0	0
T187	0	15	0	0
T188	0	22	0	0
T189	15976	0	0	0
T190	15372	0	0	0
T191	3374	0	0	0
T192	12488	0	0	0
T193	9875	0	0	0
T194	5272	0	0	0
T195	12038	0	0	0
T196	1770	0	0	0
T197	8932	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24819867	4385	0	0
T115	24244	35	0	0
T131	0	24	0	0
T181	0	15	0	0
T182	0	63	0	0
T183	0	33	0	0
T184	0	63	0	0
T185	0	23	0	0
T186	0	14	0	0
T187	0	32	0	0
T188	0	20	0	0
T189	15976	0	0	0
T190	15372	0	0	0
T191	3374	0	0	0
T192	12488	0	0	0
T193	9875	0	0	0
T194	5272	0	0	0
T195	12038	0	0	0
T196	1770	0	0	0
T197	8932	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24819867	4381	0	0
T115	24244	26	0	0
T131	0	27	0	0
T181	0	25	0	0
T182	0	38	0	0
T183	0	30	0	0
T184	0	60	0	0
T185	0	35	0	0
T186	0	17	0	0
T187	0	43	0	0
T188	0	38	0	0
T189	15976	0	0	0
T190	15372	0	0	0
T191	3374	0	0	0
T192	12488	0	0	0
T193	9875	0	0	0
T194	5272	0	0	0
T195	12038	0	0	0
T196	1770	0	0	0
T197	8932	0	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24819867	4543	0	0
T115	24244	26	0	0
T131	0	17	0	0
T181	0	25	0	0
T182	0	57	0	0
T183	0	12	0	0
T184	0	49	0	0
T185	0	14	0	0
T186	0	31	0	0
T187	0	50	0	0
T188	0	43	0	0
T189	15976	0	0	0
T190	15372	0	0	0
T191	3374	0	0	0
T192	12488	0	0	0
T193	9875	0	0	0
T194	5272	0	0	0
T195	12038	0	0	0
T196	1770	0	0	0
T197	8932	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24819867	4596	0	0
T115	24244	26	0	0
T131	0	22	0	0
T181	0	17	0	0
T182	0	80	0	0
T183	0	24	0	0
T184	0	61	0	0
T185	0	25	0	0
T186	0	23	0	0
T187	0	20	0	0
T188	0	34	0	0
T189	15976	0	0	0
T190	15372	0	0	0
T191	3374	0	0	0
T192	12488	0	0	0
T193	9875	0	0	0
T194	5272	0	0	0
T195	12038	0	0	0
T196	1770	0	0	0
T197	8932	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24819867	4568	0	0
T115	24244	21	0	0
T131	0	25	0	0
T181	0	37	0	0
T182	0	50	0	0
T183	0	30	0	0
T184	0	52	0	0
T185	0	18	0	0
T186	0	34	0	0
T187	0	22	0	0
T188	0	28	0	0
T189	15976	0	0	0
T190	15372	0	0	0
T191	3374	0	0	0
T192	12488	0	0	0
T193	9875	0	0	0
T194	5272	0	0	0
T195	12038	0	0	0
T196	1770	0	0	0
T197	8932	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24819867	4555	0	0
T115	24244	23	0	0
T131	0	31	0	0
T181	0	15	0	0
T182	0	59	0	0
T183	0	46	0	0
T184	0	61	0	0
T185	0	41	0	0
T186	0	7	0	0
T187	0	36	0	0
T188	0	43	0	0
T189	15976	0	0	0
T190	15372	0	0	0
T191	3374	0	0	0
T192	12488	0	0	0
T193	9875	0	0	0
T194	5272	0	0	0
T195	12038	0	0	0
T196	1770	0	0	0
T197	8932	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24819867	4493	0	0
T115	24244	42	0	0
T131	0	18	0	0
T181	0	46	0	0
T182	0	41	0	0
T183	0	17	0	0
T184	0	47	0	0
T185	0	22	0	0
T186	0	13	0	0
T187	0	44	0	0
T188	0	33	0	0
T189	15976	0	0	0
T190	15372	0	0	0
T191	3374	0	0	0
T192	12488	0	0	0
T193	9875	0	0	0
T194	5272	0	0	0
T195	12038	0	0	0
T196	1770	0	0	0
T197	8932	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24819867	4588	0	0
T115	24244	17	0	0
T131	0	14	0	0
T181	0	39	0	0
T182	0	44	0	0
T183	0	47	0	0
T184	0	40	0	0
T185	0	43	0	0
T186	0	14	0	0
T187	0	19	0	0
T188	0	28	0	0
T189	15976	0	0	0
T190	15372	0	0	0
T191	3374	0	0	0
T192	12488	0	0	0
T193	9875	0	0	0
T194	5272	0	0	0
T195	12038	0	0	0
T196	1770	0	0	0
T197	8932	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24819867	4542	0	0
T115	24244	25	0	0
T131	0	10	0	0
T181	0	32	0	0
T182	0	62	0	0
T183	0	17	0	0
T184	0	70	0	0
T185	0	56	0	0
T186	0	7	0	0
T187	0	52	0	0
T188	0	35	0	0
T189	15976	0	0	0
T190	15372	0	0	0
T191	3374	0	0	0
T192	12488	0	0	0
T193	9875	0	0	0
T194	5272	0	0	0
T195	12038	0	0	0
T196	1770	0	0	0
T197	8932	0	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24819867	4592	0	0
T115	24244	56	0	0
T131	0	27	0	0
T181	0	25	0	0
T182	0	58	0	0
T183	0	36	0	0
T184	0	33	0	0
T185	0	20	0	0
T186	0	17	0	0
T187	0	20	0	0
T188	0	37	0	0
T189	15976	0	0	0
T190	15372	0	0	0
T191	3374	0	0	0
T192	12488	0	0	0
T193	9875	0	0	0
T194	5272	0	0	0
T195	12038	0	0	0
T196	1770	0	0	0
T197	8932	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24819867	4558	0	0
T115	24244	29	0	0
T131	0	22	0	0
T181	0	40	0	0
T182	0	59	0	0
T183	0	31	0	0
T184	0	69	0	0
T185	0	26	0	0
T186	0	8	0	0
T187	0	44	0	0
T188	0	14	0	0
T189	15976	0	0	0
T190	15372	0	0	0
T191	3374	0	0	0
T192	12488	0	0	0
T193	9875	0	0	0
T194	5272	0	0	0
T195	12038	0	0	0
T196	1770	0	0	0
T197	8932	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24819867	4675	0	0
T115	24244	34	0	0
T131	0	38	0	0
T181	0	21	0	0
T182	0	82	0	0
T183	0	31	0	0
T184	0	58	0	0
T185	0	40	0	0
T186	0	1	0	0
T187	0	40	0	0
T188	0	29	0	0
T189	15976	0	0	0
T190	15372	0	0	0
T191	3374	0	0	0
T192	12488	0	0	0
T193	9875	0	0	0
T194	5272	0	0	0
T195	12038	0	0	0
T196	1770	0	0	0
T197	8932	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24819867	4532	0	0
T115	24244	25	0	0
T131	0	23	0	0
T181	0	28	0	0
T182	0	55	0	0
T183	0	23	0	0
T184	0	49	0	0
T185	0	22	0	0
T186	0	29	0	0
T187	0	24	0	0
T188	0	18	0	0
T189	15976	0	0	0
T190	15372	0	0	0
T191	3374	0	0	0
T192	12488	0	0	0
T193	9875	0	0	0
T194	5272	0	0	0
T195	12038	0	0	0
T196	1770	0	0	0
T197	8932	0	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24819867	4604	0	0
T115	24244	45	0	0
T131	0	24	0	0
T181	0	34	0	0
T182	0	48	0	0
T183	0	24	0	0
T184	0	45	0	0
T185	0	56	0	0
T186	0	20	0	0
T187	0	35	0	0
T188	0	18	0	0
T189	15976	0	0	0
T190	15372	0	0	0
T191	3374	0	0	0
T192	12488	0	0	0
T193	9875	0	0	0
T194	5272	0	0	0
T195	12038	0	0	0
T196	1770	0	0	0
T197	8932	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24819867	4699	0	0
T115	24244	22	0	0
T131	0	51	0	0
T181	0	33	0	0
T182	0	62	0	0
T183	0	22	0	0
T184	0	64	0	0
T185	0	12	0	0
T186	0	22	0	0
T187	0	36	0	0
T188	0	18	0	0
T189	15976	0	0	0
T190	15372	0	0	0
T191	3374	0	0	0
T192	12488	0	0	0
T193	9875	0	0	0
T194	5272	0	0	0
T195	12038	0	0	0
T196	1770	0	0	0
T197	8932	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24819867	4453	0	0
T115	24244	29	0	0
T116	0	43	0	0
T131	0	39	0	0
T181	0	23	0	0
T182	0	48	0	0
T183	0	30	0	0
T184	0	58	0	0
T185	0	42	0	0
T187	0	28	0	0
T188	0	17	0	0
T189	15976	0	0	0
T190	15372	0	0	0
T191	3374	0	0	0
T192	12488	0	0	0
T193	9875	0	0	0
T194	5272	0	0	0
T195	12038	0	0	0
T196	1770	0	0	0
T197	8932	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24819867	4635	0	0
T115	24244	44	0	0
T131	0	28	0	0
T181	0	38	0	0
T182	0	67	0	0
T183	0	41	0	0
T184	0	62	0	0
T185	0	26	0	0
T186	0	3	0	0
T187	0	19	0	0
T188	0	24	0	0
T189	15976	0	0	0
T190	15372	0	0	0
T191	3374	0	0	0
T192	12488	0	0	0
T193	9875	0	0	0
T194	5272	0	0	0
T195	12038	0	0	0
T196	1770	0	0	0
T197	8932	0	0	0