Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3166688	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

601837

1

T1

471

T2

253

T3

583

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3365031	1			T1	968		T2	2768		T3	809
values[0x0]	199252	1			T1	150		T2	62		T3	200
values[0x1]	204242	1			T1	192		T2	71		T3	208

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2169628	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1598897

1

T1

725

T2

1066

T3

737

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14496	1			T2	14		T3	7		T12	1
valid_sources[0x01]	18612	1			T2	11		T3	4		T12	2
valid_sources[0x02]	11937	1			T2	3		T3	9		T12	2
valid_sources[0x03]	12284	1			T2	9		T3	3		T12	3
valid_sources[0x04]	12872	1			T2	14		T3	6		T12	4
valid_sources[0x05]	11923	1			T2	7		T3	6		T12	1
valid_sources[0x06]	14274	1			T2	7		T3	7		T12	1
valid_sources[0x07]	13291	1			T2	10		T3	7		T12	3
valid_sources[0x08]	33819	1			T2	12		T3	6		T12	3
valid_sources[0x09]	17022	1			T2	10		T3	3		T12	1
valid_sources[0x0a]	12188	1			T2	11		T3	4		T12	1
valid_sources[0x0b]	28918	1			T2	11		T3	6		T12	3
valid_sources[0x0c]	12398	1			T2	30		T3	4		T12	3
valid_sources[0x0d]	14398	1			T2	10		T3	4		T12	2
valid_sources[0x0e]	13403	1			T2	14		T3	2		T12	7
valid_sources[0x0f]	17401	1			T2	11		T3	2		T12	1
valid_sources[0x10]	13932	1			T2	18		T3	4		T12	1
valid_sources[0x11]	17720	1			T2	7		T3	5		T12	1
valid_sources[0x12]	14159	1			T2	8		T3	5		T12	2
valid_sources[0x13]	14491	1			T2	13		T3	5		T12	2
valid_sources[0x14]	13850	1			T2	13		T3	6		T12	5
valid_sources[0x15]	15010	1			T2	13		T3	3		T12	2
valid_sources[0x16]	12330	1			T2	14		T3	5		T12	1
valid_sources[0x17]	12462	1			T2	7		T3	8		T12	3
valid_sources[0x18]	12134	1			T2	18		T3	1		T12	1
valid_sources[0x19]	15179	1			T2	9		T3	6		T14	1
valid_sources[0x1a]	14018	1			T2	8		T3	7		T12	1
valid_sources[0x1b]	23075	1			T2	13		T3	9		T12	3
valid_sources[0x1c]	12595	1			T2	3		T3	5		T13	4
valid_sources[0x1d]	12354	1			T2	12		T3	2		T12	3
valid_sources[0x1e]	14312	1			T2	8		T3	3		T12	2
valid_sources[0x1f]	12954	1			T2	14		T3	7		T14	3
valid_sources[0x20]	12377	1			T2	9		T3	2		T12	2
valid_sources[0x21]	12877	1			T2	10		T3	2		T12	2
valid_sources[0x22]	13077	1			T2	6		T3	5		T12	3
valid_sources[0x23]	13904	1			T2	9		T3	7		T12	3
valid_sources[0x24]	15619	1			T2	9		T3	8		T12	3
valid_sources[0x25]	12581	1			T2	19		T3	4		T12	1
valid_sources[0x26]	13855	1			T2	10		T3	3		T12	5
valid_sources[0x27]	17190	1			T2	17		T3	4		T12	7
valid_sources[0x28]	11993	1			T2	24		T3	2		T12	1
valid_sources[0x29]	12633	1			T2	13		T3	5		T12	2
valid_sources[0x2a]	13214	1			T2	9		T3	2		T12	3
valid_sources[0x2b]	13145	1			T2	4		T3	4		T12	6
valid_sources[0x2c]	13320	1			T2	9		T3	1		T12	1
valid_sources[0x2d]	13835	1			T2	13		T3	3		T12	8
valid_sources[0x2e]	14675	1			T2	9		T3	5		T12	3
valid_sources[0x2f]	12981	1			T2	9		T3	2		T13	2
valid_sources[0x30]	12968	1			T2	13		T3	8		T12	1
valid_sources[0x31]	13562	1			T2	15		T3	3		T12	1
valid_sources[0x32]	12291	1			T2	14		T3	3		T12	2
valid_sources[0x33]	14340	1			T2	11		T3	8		T12	1
valid_sources[0x34]	12876	1			T2	16		T3	3		T12	2
valid_sources[0x35]	12273	1			T2	7		T3	6		T12	4
valid_sources[0x36]	16495	1			T2	11		T3	6		T12	2
valid_sources[0x37]	16511	1			T2	19		T3	6		T12	1
valid_sources[0x38]	12797	1			T2	8		T3	4		T12	3
valid_sources[0x39]	12803	1			T2	8		T3	5		T12	1
valid_sources[0x3a]	12956	1			T2	9		T3	1		T12	2
valid_sources[0x3b]	13084	1			T2	15		T3	2		T12	2
valid_sources[0x3c]	12601	1			T2	2		T3	3		T12	1
valid_sources[0x3d]	14318	1			T2	20		T3	2		T12	4
valid_sources[0x3e]	12448	1			T2	6		T3	6		T12	1
valid_sources[0x3f]	13256	1			T2	13		T3	5		T12	6
valid_sources[0x40]	13876	1			T2	13		T3	5		T12	2
valid_sources[0x41]	12773	1			T2	8		T3	2		T12	3
valid_sources[0x42]	17809	1			T2	15		T3	3		T12	2
valid_sources[0x43]	14344	1			T2	11		T3	4		T12	3
valid_sources[0x44]	12894	1			T2	13		T3	3		T17	3
valid_sources[0x45]	13728	1			T2	18		T3	9		T12	4
valid_sources[0x46]	19678	1			T2	19		T3	6		T12	3
valid_sources[0x47]	14470	1			T2	12		T3	8		T14	120
valid_sources[0x48]	13369	1			T2	14		T12	1		T13	2
valid_sources[0x49]	13129	1			T2	11		T3	3		T12	1
valid_sources[0x4a]	14917	1			T2	14		T3	4		T14	25
valid_sources[0x4b]	13517	1			T2	10		T3	3		T13	3
valid_sources[0x4c]	13138	1			T2	5		T3	8		T12	2
valid_sources[0x4d]	12698	1			T2	8		T3	10		T12	3
valid_sources[0x4e]	13682	1			T2	9		T3	5		T12	4
valid_sources[0x4f]	14460	1			T2	7		T3	4		T12	5
valid_sources[0x50]	13047	1			T2	13		T3	8		T12	1
valid_sources[0x51]	12389	1			T2	9		T3	10		T12	2
valid_sources[0x52]	13362	1			T2	12		T3	7		T12	1
valid_sources[0x53]	12823	1			T2	13		T3	2		T12	1
valid_sources[0x54]	12202	1			T2	5		T3	2		T12	1
valid_sources[0x55]	12429	1			T2	15		T3	3		T12	3
valid_sources[0x56]	12351	1			T2	16		T3	3		T12	2
valid_sources[0x57]	15598	1			T2	24		T3	3		T12	2
valid_sources[0x58]	13032	1			T2	13		T3	4		T12	3
valid_sources[0x59]	12558	1			T2	7		T3	6		T12	5
valid_sources[0x5a]	14232	1			T2	15		T3	4		T12	2
valid_sources[0x5b]	13980	1			T2	15		T3	4		T12	1
valid_sources[0x5c]	24684	1			T2	17		T3	5		T15	8
valid_sources[0x5d]	16187	1			T2	16		T3	5		T12	1
valid_sources[0x5e]	13881	1			T2	15		T3	6		T12	2
valid_sources[0x5f]	13606	1			T2	10		T3	3		T13	2
valid_sources[0x60]	15518	1			T2	11		T3	10		T12	1
valid_sources[0x61]	13466	1			T2	13		T3	3		T12	1
valid_sources[0x62]	11940	1			T2	8		T3	2		T12	1
valid_sources[0x63]	12829	1			T2	18		T3	6		T12	1
valid_sources[0x64]	12787	1			T2	9		T12	1		T13	2
valid_sources[0x65]	12652	1			T2	8		T3	5		T12	1
valid_sources[0x66]	13328	1			T2	9		T3	3		T12	4
valid_sources[0x67]	13272	1			T2	23		T3	7		T12	2
valid_sources[0x68]	13188	1			T2	14		T3	7		T12	2
valid_sources[0x69]	13290	1			T2	8		T3	5		T12	5
valid_sources[0x6a]	44293	1			T2	7		T3	5		T12	1
valid_sources[0x6b]	14706	1			T2	8		T3	5		T12	2
valid_sources[0x6c]	13944	1			T2	7		T3	3		T12	2
valid_sources[0x6d]	15223	1			T1	1310		T2	5		T3	9
valid_sources[0x6e]	13119	1			T2	14		T3	8		T12	1
valid_sources[0x6f]	12329	1			T2	11		T3	10		T14	1
valid_sources[0x70]	13931	1			T2	13		T3	4		T12	2
valid_sources[0x71]	12538	1			T2	8		T3	7		T12	5
valid_sources[0x72]	15422	1			T2	9		T3	10		T12	1
valid_sources[0x73]	14893	1			T2	16		T3	3		T13	2
valid_sources[0x74]	18397	1			T2	5		T3	7		T15	5
valid_sources[0x75]	12831	1			T2	11		T3	7		T12	4
valid_sources[0x76]	13098	1			T2	15		T3	3		T12	3
valid_sources[0x77]	13565	1			T2	16		T3	4		T12	2
valid_sources[0x78]	21770	1			T2	11		T3	8		T12	2
valid_sources[0x79]	64959	1			T2	16		T3	3		T15	3
valid_sources[0x7a]	12627	1			T2	20		T3	7		T12	3
valid_sources[0x7b]	13090	1			T2	10		T3	7		T12	2
valid_sources[0x7c]	13312	1			T2	10		T3	5		T12	2
valid_sources[0x7d]	13317	1			T2	14		T3	5		T12	1
valid_sources[0x7e]	16429	1			T2	16		T3	4		T12	1
valid_sources[0x7f]	15586	1			T2	9		T3	2		T12	2
valid_sources[0x80]	12340	1			T2	4		T3	1		T12	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

326951

1

T1

220

T2

216

T3

326

values[0x0]

all_enables

biggest_size

143995

1

T1

109

T2

24

T3

135

values[0x1]

all_enables

biggest_size

130891

1

T1

142

T2

13

T3

122