Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	23295938	17566	0	0
attest_sw_binding_0_rd_A	23295938	1768	0	0
attest_sw_binding_1_rd_A	23295938	1672	0	0
attest_sw_binding_2_rd_A	23295938	1754	0	0
attest_sw_binding_3_rd_A	23295938	1780	0	0
attest_sw_binding_4_rd_A	23295938	1580	0	0
attest_sw_binding_5_rd_A	23295938	1608	0	0
attest_sw_binding_6_rd_A	23295938	1632	0	0
attest_sw_binding_7_rd_A	23295938	1601	0	0
intr_enable_rd_A	23295938	2159	0	0
key_version_rd_A	23295938	1816	0	0
max_creator_key_ver_regwen_rd_A	23295938	1824	0	0
max_owner_int_key_ver_regwen_rd_A	23295938	1782	0	0
max_owner_key_ver_regwen_rd_A	23295938	1676	0	0
reseed_interval_regwen_rd_A	23295938	1822	0	0
salt_0_rd_A	23295938	1731	0	0
salt_1_rd_A	23295938	1743	0	0
salt_2_rd_A	23295938	1676	0	0
salt_3_rd_A	23295938	1793	0	0
salt_4_rd_A	23295938	1644	0	0
salt_5_rd_A	23295938	1734	0	0
salt_6_rd_A	23295938	1691	0	0
salt_7_rd_A	23295938	1613	0	0
sealing_sw_binding_0_rd_A	23295938	1579	0	0
sealing_sw_binding_1_rd_A	23295938	1674	0	0
sealing_sw_binding_2_rd_A	23295938	1586	0	0
sealing_sw_binding_3_rd_A	23295938	1731	0	0
sealing_sw_binding_4_rd_A	23295938	1558	0	0
sealing_sw_binding_5_rd_A	23295938	1716	0	0
sealing_sw_binding_6_rd_A	23295938	1700	0	0
sealing_sw_binding_7_rd_A	23295938	1576	0	0
sideload_clear_rd_A	23295938	1637	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23295938	17566	0	0
T18	53805	150	0	0
T19	27655	0	0	0
T34	5338	0	0	0
T35	3829	0	0	0
T37	11106	0	0	0
T38	2663	0	0	0
T45	2357	0	0	0
T46	0	415	0	0
T49	4055	0	0	0
T50	0	490	0	0
T54	0	97	0	0
T56	0	426	0	0
T69	0	181	0	0
T72	0	164	0	0
T118	0	226	0	0
T125	0	1153	0	0
T126	9115	0	0	0
T127	4982	0	0	0
T129	0	66	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23295938	1768	0	0
T25	5456	0	0	0
T72	19394	28	0	0
T91	10152	0	0	0
T119	0	34	0	0
T129	0	24	0	0
T161	0	96	0	0
T178	0	36	0	0
T179	0	25	0	0
T180	0	31	0	0
T181	0	38	0	0
T182	0	27	0	0
T183	0	21	0	0
T184	3883	0	0	0
T185	15487	0	0	0
T186	20571	0	0	0
T187	5655	0	0	0
T188	22572	0	0	0
T189	4035	0	0	0
T190	10960	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23295938	1672	0	0
T25	5456	0	0	0
T72	19394	22	0	0
T91	10152	0	0	0
T119	0	23	0	0
T129	0	26	0	0
T161	0	92	0	0
T178	0	30	0	0
T179	0	17	0	0
T180	0	47	0	0
T181	0	31	0	0
T182	0	24	0	0
T183	0	19	0	0
T184	3883	0	0	0
T185	15487	0	0	0
T186	20571	0	0	0
T187	5655	0	0	0
T188	22572	0	0	0
T189	4035	0	0	0
T190	10960	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23295938	1754	0	0
T25	5456	0	0	0
T59	0	1	0	0
T72	19394	15	0	0
T91	10152	0	0	0
T119	0	28	0	0
T129	0	28	0	0
T178	0	30	0	0
T179	0	21	0	0
T180	0	13	0	0
T181	0	46	0	0
T182	0	23	0	0
T183	0	39	0	0
T184	3883	0	0	0
T185	15487	0	0	0
T186	20571	0	0	0
T187	5655	0	0	0
T188	22572	0	0	0
T189	4035	0	0	0
T190	10960	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23295938	1780	0	0
T25	5456	0	0	0
T72	19394	47	0	0
T91	10152	0	0	0
T119	0	27	0	0
T129	0	20	0	0
T161	0	93	0	0
T178	0	46	0	0
T179	0	32	0	0
T180	0	28	0	0
T181	0	38	0	0
T182	0	20	0	0
T183	0	35	0	0
T184	3883	0	0	0
T185	15487	0	0	0
T186	20571	0	0	0
T187	5655	0	0	0
T188	22572	0	0	0
T189	4035	0	0	0
T190	10960	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23295938	1580	0	0
T25	5456	0	0	0
T72	19394	24	0	0
T91	10152	0	0	0
T119	0	31	0	0
T129	0	17	0	0
T161	0	78	0	0
T178	0	70	0	0
T179	0	18	0	0
T180	0	27	0	0
T181	0	42	0	0
T182	0	34	0	0
T183	0	27	0	0
T184	3883	0	0	0
T185	15487	0	0	0
T186	20571	0	0	0
T187	5655	0	0	0
T188	22572	0	0	0
T189	4035	0	0	0
T190	10960	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23295938	1608	0	0
T25	5456	0	0	0
T72	19394	43	0	0
T91	10152	0	0	0
T119	0	31	0	0
T129	0	32	0	0
T161	0	59	0	0
T178	0	37	0	0
T179	0	29	0	0
T180	0	34	0	0
T181	0	23	0	0
T182	0	28	0	0
T183	0	18	0	0
T184	3883	0	0	0
T185	15487	0	0	0
T186	20571	0	0	0
T187	5655	0	0	0
T188	22572	0	0	0
T189	4035	0	0	0
T190	10960	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23295938	1632	0	0
T25	5456	0	0	0
T72	19394	30	0	0
T91	10152	0	0	0
T119	0	31	0	0
T129	0	39	0	0
T161	0	87	0	0
T178	0	25	0	0
T179	0	24	0	0
T180	0	30	0	0
T181	0	21	0	0
T182	0	23	0	0
T183	0	21	0	0
T184	3883	0	0	0
T185	15487	0	0	0
T186	20571	0	0	0
T187	5655	0	0	0
T188	22572	0	0	0
T189	4035	0	0	0
T190	10960	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23295938	1601	0	0
T25	5456	0	0	0
T72	19394	38	0	0
T91	10152	0	0	0
T119	0	31	0	0
T129	0	32	0	0
T161	0	66	0	0
T178	0	53	0	0
T179	0	30	0	0
T180	0	11	0	0
T181	0	17	0	0
T182	0	29	0	0
T183	0	29	0	0
T184	3883	0	0	0
T185	15487	0	0	0
T186	20571	0	0	0
T187	5655	0	0	0
T188	22572	0	0	0
T189	4035	0	0	0
T190	10960	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23295938	2159	0	0
T20	3482	0	0	0
T36	7252	0	0	0
T40	9162	0	0	0
T47	504192	20	0	0
T48	6640	0	0	0
T72	0	37	0	0
T73	0	27	0	0
T105	849	0	0	0
T107	44635	6	0	0
T129	0	25	0	0
T178	0	35	0	0
T179	0	50	0	0
T191	0	10	0	0
T192	0	23	0	0
T193	0	52	0	0
T194	4395	0	0	0
T195	10442	0	0	0
T196	2968	0	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23295938	1816	0	0
T25	5456	0	0	0
T72	19394	26	0	0
T91	10152	0	0	0
T119	0	28	0	0
T129	0	31	0	0
T161	0	88	0	0
T178	0	24	0	0
T179	0	25	0	0
T180	0	19	0	0
T181	0	26	0	0
T182	0	50	0	0
T183	0	26	0	0
T184	3883	0	0	0
T185	15487	0	0	0
T186	20571	0	0	0
T187	5655	0	0	0
T188	22572	0	0	0
T189	4035	0	0	0
T190	10960	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23295938	1824	0	0
T25	5456	0	0	0
T72	19394	27	0	0
T91	10152	0	0	0
T119	0	30	0	0
T129	0	32	0	0
T161	0	85	0	0
T178	0	19	0	0
T179	0	30	0	0
T180	0	22	0	0
T181	0	30	0	0
T182	0	46	0	0
T183	0	58	0	0
T184	3883	0	0	0
T185	15487	0	0	0
T186	20571	0	0	0
T187	5655	0	0	0
T188	22572	0	0	0
T189	4035	0	0	0
T190	10960	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23295938	1782	0	0
T25	5456	0	0	0
T72	19394	25	0	0
T91	10152	0	0	0
T119	0	24	0	0
T129	0	11	0	0
T161	0	89	0	0
T178	0	56	0	0
T179	0	16	0	0
T180	0	38	0	0
T181	0	28	0	0
T182	0	26	0	0
T183	0	34	0	0
T184	3883	0	0	0
T185	15487	0	0	0
T186	20571	0	0	0
T187	5655	0	0	0
T188	22572	0	0	0
T189	4035	0	0	0
T190	10960	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23295938	1676	0	0
T25	5456	0	0	0
T72	19394	34	0	0
T91	10152	0	0	0
T119	0	14	0	0
T129	0	19	0	0
T161	0	74	0	0
T178	0	40	0	0
T179	0	26	0	0
T180	0	41	0	0
T181	0	18	0	0
T182	0	39	0	0
T183	0	29	0	0
T184	3883	0	0	0
T185	15487	0	0	0
T186	20571	0	0	0
T187	5655	0	0	0
T188	22572	0	0	0
T189	4035	0	0	0
T190	10960	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23295938	1822	0	0
T25	5456	0	0	0
T72	19394	25	0	0
T91	10152	0	0	0
T119	0	28	0	0
T129	0	18	0	0
T161	0	94	0	0
T178	0	50	0	0
T179	0	35	0	0
T180	0	40	0	0
T181	0	46	0	0
T182	0	27	0	0
T183	0	47	0	0
T184	3883	0	0	0
T185	15487	0	0	0
T186	20571	0	0	0
T187	5655	0	0	0
T188	22572	0	0	0
T189	4035	0	0	0
T190	10960	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23295938	1731	0	0
T25	5456	0	0	0
T72	19394	38	0	0
T91	10152	0	0	0
T119	0	7	0	0
T129	0	32	0	0
T161	0	92	0	0
T178	0	44	0	0
T179	0	47	0	0
T180	0	46	0	0
T181	0	22	0	0
T182	0	2	0	0
T183	0	35	0	0
T184	3883	0	0	0
T185	15487	0	0	0
T186	20571	0	0	0
T187	5655	0	0	0
T188	22572	0	0	0
T189	4035	0	0	0
T190	10960	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23295938	1743	0	0
T25	5456	0	0	0
T72	19394	45	0	0
T91	10152	0	0	0
T119	0	20	0	0
T129	0	22	0	0
T161	0	78	0	0
T178	0	15	0	0
T179	0	29	0	0
T180	0	37	0	0
T181	0	27	0	0
T182	0	41	0	0
T183	0	32	0	0
T184	3883	0	0	0
T185	15487	0	0	0
T186	20571	0	0	0
T187	5655	0	0	0
T188	22572	0	0	0
T189	4035	0	0	0
T190	10960	0	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23295938	1676	0	0
T25	5456	0	0	0
T72	19394	38	0	0
T91	10152	0	0	0
T119	0	34	0	0
T129	0	20	0	0
T161	0	75	0	0
T178	0	29	0	0
T179	0	23	0	0
T180	0	20	0	0
T181	0	32	0	0
T182	0	19	0	0
T183	0	18	0	0
T184	3883	0	0	0
T185	15487	0	0	0
T186	20571	0	0	0
T187	5655	0	0	0
T188	22572	0	0	0
T189	4035	0	0	0
T190	10960	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23295938	1793	0	0
T25	5456	0	0	0
T72	19394	47	0	0
T91	10152	0	0	0
T119	0	27	0	0
T129	0	38	0	0
T161	0	78	0	0
T178	0	23	0	0
T179	0	19	0	0
T180	0	49	0	0
T181	0	36	0	0
T182	0	22	0	0
T183	0	31	0	0
T184	3883	0	0	0
T185	15487	0	0	0
T186	20571	0	0	0
T187	5655	0	0	0
T188	22572	0	0	0
T189	4035	0	0	0
T190	10960	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23295938	1644	0	0
T25	5456	0	0	0
T72	19394	27	0	0
T91	10152	0	0	0
T119	0	27	0	0
T129	0	26	0	0
T161	0	78	0	0
T178	0	36	0	0
T179	0	36	0	0
T180	0	21	0	0
T181	0	35	0	0
T182	0	17	0	0
T183	0	26	0	0
T184	3883	0	0	0
T185	15487	0	0	0
T186	20571	0	0	0
T187	5655	0	0	0
T188	22572	0	0	0
T189	4035	0	0	0
T190	10960	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23295938	1734	0	0
T25	5456	0	0	0
T72	19394	25	0	0
T91	10152	0	0	0
T119	0	34	0	0
T129	0	34	0	0
T161	0	83	0	0
T178	0	15	0	0
T179	0	25	0	0
T180	0	24	0	0
T181	0	27	0	0
T182	0	27	0	0
T183	0	49	0	0
T184	3883	0	0	0
T185	15487	0	0	0
T186	20571	0	0	0
T187	5655	0	0	0
T188	22572	0	0	0
T189	4035	0	0	0
T190	10960	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23295938	1691	0	0
T25	5456	0	0	0
T72	19394	18	0	0
T91	10152	0	0	0
T119	0	33	0	0
T129	0	16	0	0
T161	0	74	0	0
T178	0	39	0	0
T179	0	43	0	0
T180	0	29	0	0
T181	0	25	0	0
T182	0	23	0	0
T183	0	29	0	0
T184	3883	0	0	0
T185	15487	0	0	0
T186	20571	0	0	0
T187	5655	0	0	0
T188	22572	0	0	0
T189	4035	0	0	0
T190	10960	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23295938	1613	0	0
T25	5456	0	0	0
T72	19394	23	0	0
T91	10152	0	0	0
T119	0	25	0	0
T129	0	43	0	0
T161	0	80	0	0
T178	0	29	0	0
T179	0	31	0	0
T180	0	30	0	0
T181	0	39	0	0
T182	0	18	0	0
T183	0	23	0	0
T184	3883	0	0	0
T185	15487	0	0	0
T186	20571	0	0	0
T187	5655	0	0	0
T188	22572	0	0	0
T189	4035	0	0	0
T190	10960	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23295938	1579	0	0
T25	5456	0	0	0
T72	19394	15	0	0
T91	10152	0	0	0
T119	0	20	0	0
T129	0	18	0	0
T161	0	61	0	0
T178	0	20	0	0
T179	0	16	0	0
T180	0	15	0	0
T181	0	33	0	0
T182	0	39	0	0
T183	0	24	0	0
T184	3883	0	0	0
T185	15487	0	0	0
T186	20571	0	0	0
T187	5655	0	0	0
T188	22572	0	0	0
T189	4035	0	0	0
T190	10960	0	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23295938	1674	0	0
T25	5456	0	0	0
T72	19394	31	0	0
T91	10152	0	0	0
T119	0	26	0	0
T129	0	33	0	0
T161	0	86	0	0
T178	0	19	0	0
T179	0	24	0	0
T180	0	26	0	0
T181	0	42	0	0
T182	0	18	0	0
T183	0	8	0	0
T184	3883	0	0	0
T185	15487	0	0	0
T186	20571	0	0	0
T187	5655	0	0	0
T188	22572	0	0	0
T189	4035	0	0	0
T190	10960	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23295938	1586	0	0
T25	5456	0	0	0
T72	19394	30	0	0
T91	10152	0	0	0
T119	0	32	0	0
T129	0	25	0	0
T161	0	96	0	0
T178	0	10	0	0
T179	0	32	0	0
T180	0	25	0	0
T181	0	33	0	0
T182	0	32	0	0
T183	0	25	0	0
T184	3883	0	0	0
T185	15487	0	0	0
T186	20571	0	0	0
T187	5655	0	0	0
T188	22572	0	0	0
T189	4035	0	0	0
T190	10960	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23295938	1731	0	0
T25	5456	0	0	0
T72	19394	45	0	0
T91	10152	0	0	0
T119	0	32	0	0
T129	0	20	0	0
T161	0	66	0	0
T178	0	27	0	0
T179	0	20	0	0
T180	0	25	0	0
T181	0	23	0	0
T182	0	29	0	0
T183	0	42	0	0
T184	3883	0	0	0
T185	15487	0	0	0
T186	20571	0	0	0
T187	5655	0	0	0
T188	22572	0	0	0
T189	4035	0	0	0
T190	10960	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23295938	1558	0	0
T25	5456	0	0	0
T72	19394	20	0	0
T91	10152	0	0	0
T119	0	32	0	0
T129	0	20	0	0
T161	0	78	0	0
T178	0	32	0	0
T179	0	10	0	0
T180	0	17	0	0
T181	0	23	0	0
T182	0	28	0	0
T183	0	15	0	0
T184	3883	0	0	0
T185	15487	0	0	0
T186	20571	0	0	0
T187	5655	0	0	0
T188	22572	0	0	0
T189	4035	0	0	0
T190	10960	0	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23295938	1716	0	0
T25	5456	0	0	0
T72	19394	32	0	0
T91	10152	0	0	0
T119	0	30	0	0
T129	0	27	0	0
T161	0	90	0	0
T178	0	43	0	0
T179	0	32	0	0
T180	0	30	0	0
T181	0	26	0	0
T182	0	40	0	0
T183	0	24	0	0
T184	3883	0	0	0
T185	15487	0	0	0
T186	20571	0	0	0
T187	5655	0	0	0
T188	22572	0	0	0
T189	4035	0	0	0
T190	10960	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23295938	1700	0	0
T25	5456	0	0	0
T72	19394	44	0	0
T91	10152	0	0	0
T119	0	23	0	0
T129	0	36	0	0
T161	0	75	0	0
T178	0	28	0	0
T179	0	18	0	0
T180	0	22	0	0
T181	0	15	0	0
T182	0	21	0	0
T183	0	41	0	0
T184	3883	0	0	0
T185	15487	0	0	0
T186	20571	0	0	0
T187	5655	0	0	0
T188	22572	0	0	0
T189	4035	0	0	0
T190	10960	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23295938	1576	0	0
T25	5456	0	0	0
T72	19394	38	0	0
T91	10152	0	0	0
T119	0	29	0	0
T129	0	21	0	0
T161	0	54	0	0
T178	0	37	0	0
T179	0	20	0	0
T180	0	43	0	0
T181	0	19	0	0
T182	0	27	0	0
T183	0	26	0	0
T184	3883	0	0	0
T185	15487	0	0	0
T186	20571	0	0	0
T187	5655	0	0	0
T188	22572	0	0	0
T189	4035	0	0	0
T190	10960	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23295938	1637	0	0
T25	5456	0	0	0
T72	19394	30	0	0
T91	10152	0	0	0
T119	0	18	0	0
T129	0	13	0	0
T161	0	84	0	0
T178	0	38	0	0
T179	0	35	0	0
T180	0	7	0	0
T181	0	37	0	0
T182	0	12	0	0
T183	0	33	0	0
T184	3883	0	0	0
T185	15487	0	0	0
T186	20571	0	0	0
T187	5655	0	0	0
T188	22572	0	0	0
T189	4035	0	0	0
T190	10960	0	0	0