Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3321824	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

645721

1

T1

998

T2

150

T3

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3538763	1			T1	1432		T2	304		T3	1
values[0x0]	213162	1			T1	346		T2	49		T3	1
values[0x1]	215620	1			T1	347		T2	38		T3	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2275858	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1691687

1

T1

1254

T2

209

T3

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9991	1			T1	16		T17	19		T19	61
valid_sources[0x01]	10108	1			T1	6		T2	1		T14	5
valid_sources[0x02]	11664	1			T1	10		T2	2		T14	10
valid_sources[0x03]	11249	1			T1	9		T14	3		T15	4
valid_sources[0x04]	14109	1			T1	9		T15	4		T17	9
valid_sources[0x05]	11171	1			T1	6		T2	2		T14	3
valid_sources[0x06]	10566	1			T1	6		T4	1		T14	1
valid_sources[0x07]	10423	1			T1	6		T15	3		T17	10
valid_sources[0x08]	20613	1			T1	8		T2	3		T14	5
valid_sources[0x09]	11539	1			T1	7		T2	7		T14	9
valid_sources[0x0a]	11365	1			T1	7		T14	6		T15	1
valid_sources[0x0b]	10917	1			T1	13		T2	4		T14	4
valid_sources[0x0c]	11551	1			T1	11		T2	1		T17	12
valid_sources[0x0d]	13095	1			T1	8		T17	3		T18	1001
valid_sources[0x0e]	10724	1			T1	12		T2	1		T14	1
valid_sources[0x0f]	23290	1			T1	8		T14	1		T15	1
valid_sources[0x10]	22571	1			T1	9		T2	1		T14	5
valid_sources[0x11]	12229	1			T1	8		T2	1		T14	3
valid_sources[0x12]	13124	1			T1	5		T14	1		T15	3
valid_sources[0x13]	11972	1			T1	4		T2	3		T14	7
valid_sources[0x14]	14796	1			T1	9		T2	2		T14	5
valid_sources[0x15]	11756	1			T1	5		T2	1		T14	2
valid_sources[0x16]	11663	1			T1	7		T2	2		T14	7
valid_sources[0x17]	10918	1			T1	8		T2	2		T14	1
valid_sources[0x18]	11983	1			T1	5		T2	2		T15	3
valid_sources[0x19]	11778	1			T1	9		T2	1		T4	7
valid_sources[0x1a]	16206	1			T1	11		T15	2		T17	6
valid_sources[0x1b]	10051	1			T1	12		T15	4		T17	10
valid_sources[0x1c]	21288	1			T1	8		T4	196		T14	17
valid_sources[0x1d]	12883	1			T1	9		T14	2		T17	18
valid_sources[0x1e]	33478	1			T1	10		T2	3		T17	16
valid_sources[0x1f]	20549	1			T1	10		T3	1		T17	3
valid_sources[0x20]	10135	1			T1	10		T2	1		T14	2
valid_sources[0x21]	13746	1			T1	8		T2	2		T14	6
valid_sources[0x22]	11456	1			T1	10		T2	2		T14	3
valid_sources[0x23]	17293	1			T1	13		T2	3		T4	8
valid_sources[0x24]	10840	1			T1	7		T2	4		T14	3
valid_sources[0x25]	12107	1			T1	11		T2	1		T14	10
valid_sources[0x26]	9975	1			T1	4		T17	34		T19	64
valid_sources[0x27]	11560	1			T1	17		T14	1		T17	24
valid_sources[0x28]	42105	1			T1	6		T2	1		T4	32
valid_sources[0x29]	10884	1			T1	11		T2	4		T14	4
valid_sources[0x2a]	10650	1			T1	11		T2	2		T14	7
valid_sources[0x2b]	24965	1			T1	7		T14	3		T17	14
valid_sources[0x2c]	10707	1			T1	12		T2	2		T4	21
valid_sources[0x2d]	15197	1			T1	5		T14	1		T17	15
valid_sources[0x2e]	11480	1			T1	10		T2	5		T14	5
valid_sources[0x2f]	11714	1			T1	12		T14	2		T15	4
valid_sources[0x30]	13238	1			T1	8		T2	5		T14	5
valid_sources[0x31]	10326	1			T1	6		T2	2		T15	1
valid_sources[0x32]	28369	1			T1	5		T2	2		T14	7
valid_sources[0x33]	11934	1			T1	8		T2	6		T15	1
valid_sources[0x34]	16626	1			T1	10		T14	2		T15	2
valid_sources[0x35]	11461	1			T1	12		T2	3		T14	1
valid_sources[0x36]	11236	1			T1	7		T2	2		T14	3
valid_sources[0x37]	13622	1			T1	6		T2	3		T15	1
valid_sources[0x38]	11054	1			T1	9		T14	2		T15	3
valid_sources[0x39]	11279	1			T1	6		T2	1		T14	2
valid_sources[0x3a]	13047	1			T1	7		T2	1		T17	20
valid_sources[0x3b]	10871	1			T1	9		T2	3		T15	2
valid_sources[0x3c]	12373	1			T1	11		T4	59		T15	3
valid_sources[0x3d]	10221	1			T1	8		T14	2		T15	2
valid_sources[0x3e]	30861	1			T1	9		T2	1		T14	3
valid_sources[0x3f]	14362	1			T1	13		T2	5		T17	4
valid_sources[0x40]	10804	1			T1	6		T14	3		T15	4
valid_sources[0x41]	60636	1			T1	5		T4	2		T14	4
valid_sources[0x42]	14007	1			T1	5		T2	2		T14	2
valid_sources[0x43]	10324	1			T1	6		T2	2		T14	3
valid_sources[0x44]	10396	1			T1	4		T14	8		T15	2
valid_sources[0x45]	14128	1			T1	10		T14	1		T15	3
valid_sources[0x46]	14809	1			T1	7		T2	1		T14	1
valid_sources[0x47]	11651	1			T1	9		T17	9		T19	66
valid_sources[0x48]	11253	1			T1	7		T17	13		T19	81
valid_sources[0x49]	21835	1			T1	5		T2	1		T14	2
valid_sources[0x4a]	11270	1			T1	5		T2	1		T14	1
valid_sources[0x4b]	17695	1			T1	10		T14	4		T15	4
valid_sources[0x4c]	10704	1			T1	5		T2	1		T14	2
valid_sources[0x4d]	16004	1			T1	10		T4	192		T14	1
valid_sources[0x4e]	26863	1			T1	15		T2	3		T17	16
valid_sources[0x4f]	38966	1			T1	7		T2	6		T4	24
valid_sources[0x50]	10736	1			T1	12		T2	4		T15	3
valid_sources[0x51]	11444	1			T1	11		T2	3		T4	2
valid_sources[0x52]	11473	1			T1	7		T2	2		T14	3
valid_sources[0x53]	11044	1			T1	8		T2	1		T14	2
valid_sources[0x54]	39363	1			T1	6		T2	3		T4	1264
valid_sources[0x55]	12049	1			T1	12		T15	2		T17	25
valid_sources[0x56]	14197	1			T1	2		T14	4		T15	2
valid_sources[0x57]	14146	1			T1	10		T2	3		T15	5
valid_sources[0x58]	11478	1			T1	6		T2	1		T17	14
valid_sources[0x59]	10466	1			T1	8		T2	1		T17	26
valid_sources[0x5a]	10479	1			T1	6		T2	6		T14	8
valid_sources[0x5b]	19058	1			T1	6		T2	2		T14	3
valid_sources[0x5c]	12260	1			T1	5		T14	1		T15	2
valid_sources[0x5d]	16404	1			T1	10		T2	2		T4	2
valid_sources[0x5e]	11345	1			T1	15		T15	2		T17	16
valid_sources[0x5f]	11375	1			T1	7		T2	2		T15	8
valid_sources[0x60]	12232	1			T1	8		T2	2		T14	1
valid_sources[0x61]	12405	1			T1	7		T14	3		T15	1
valid_sources[0x62]	200967	1			T1	9		T2	1		T15	3
valid_sources[0x63]	10900	1			T1	4		T2	10		T14	4
valid_sources[0x64]	11992	1			T1	6		T4	16		T14	11
valid_sources[0x65]	11161	1			T1	5		T2	2		T4	23
valid_sources[0x66]	12240	1			T1	11		T2	4		T14	7
valid_sources[0x67]	10950	1			T1	8		T14	1		T15	2
valid_sources[0x68]	11342	1			T1	10		T14	5		T15	2
valid_sources[0x69]	15627	1			T1	8		T15	1		T17	18
valid_sources[0x6a]	10680	1			T1	9		T2	4		T14	3
valid_sources[0x6b]	24934	1			T1	12		T14	7		T15	1
valid_sources[0x6c]	14393	1			T1	9		T2	3		T15	2
valid_sources[0x6d]	12957	1			T1	9		T17	17		T19	73
valid_sources[0x6e]	11121	1			T1	7		T2	1		T14	10
valid_sources[0x6f]	15149	1			T1	6		T2	2		T4	53
valid_sources[0x70]	19944	1			T1	10		T2	1		T14	10
valid_sources[0x71]	10558	1			T1	8		T2	2		T14	3
valid_sources[0x72]	14937	1			T1	12		T2	2		T14	1
valid_sources[0x73]	45256	1			T1	9		T2	2		T14	2
valid_sources[0x74]	10387	1			T1	7		T2	3		T14	2
valid_sources[0x75]	11249	1			T1	7		T2	1		T14	5
valid_sources[0x76]	13259	1			T1	14		T17	17		T19	76
valid_sources[0x77]	11082	1			T1	14		T2	3		T4	1
valid_sources[0x78]	10907	1			T1	10		T17	12		T19	65
valid_sources[0x79]	14098	1			T1	7		T2	3		T4	14
valid_sources[0x7a]	18468	1			T1	4		T2	1		T4	28
valid_sources[0x7b]	13250	1			T1	8		T14	1		T17	20
valid_sources[0x7c]	11660	1			T1	7		T2	5		T14	1
valid_sources[0x7d]	11432	1			T1	14		T14	1		T17	8
valid_sources[0x7e]	10731	1			T1	11		T2	1		T14	2
valid_sources[0x7f]	16329	1			T1	5		T2	2		T14	1
valid_sources[0x80]	11196	1			T1	8		T2	1		T15	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

353807

1

T1

613

T2

125

T3

1

values[0x0]

all_enables

biggest_size

153328

1

T1

215

T2

18

T3

1

values[0x1]

all_enables

biggest_size

138586

1

T1

170

T2

7

T4

368