Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	25722340	13413	0	0
attest_sw_binding_0_rd_A	25722340	3640	0	0
attest_sw_binding_1_rd_A	25722340	3796	0	0
attest_sw_binding_2_rd_A	25722340	3787	0	0
attest_sw_binding_3_rd_A	25722340	3795	0	0
attest_sw_binding_4_rd_A	25722340	3792	0	0
attest_sw_binding_5_rd_A	25722340	3795	0	0
attest_sw_binding_6_rd_A	25722340	3834	0	0
attest_sw_binding_7_rd_A	25722340	3850	0	0
intr_enable_rd_A	25722340	4341	0	0
key_version_rd_A	25722340	3517	0	0
max_creator_key_ver_regwen_rd_A	25722340	3908	0	0
max_owner_int_key_ver_regwen_rd_A	25722340	3541	0	0
max_owner_key_ver_regwen_rd_A	25722340	3724	0	0
reseed_interval_regwen_rd_A	25722340	3901	0	0
salt_0_rd_A	25722340	3625	0	0
salt_1_rd_A	25722340	3752	0	0
salt_2_rd_A	25722340	3805	0	0
salt_3_rd_A	25722340	3754	0	0
salt_4_rd_A	25722340	3754	0	0
salt_5_rd_A	25722340	3920	0	0
salt_6_rd_A	25722340	3784	0	0
salt_7_rd_A	25722340	3636	0	0
sealing_sw_binding_0_rd_A	25722340	3818	0	0
sealing_sw_binding_1_rd_A	25722340	3713	0	0
sealing_sw_binding_2_rd_A	25722340	3621	0	0
sealing_sw_binding_3_rd_A	25722340	3806	0	0
sealing_sw_binding_4_rd_A	25722340	3810	0	0
sealing_sw_binding_5_rd_A	25722340	3750	0	0
sealing_sw_binding_6_rd_A	25722340	3590	0	0
sealing_sw_binding_7_rd_A	25722340	3716	0	0
sideload_clear_rd_A	25722340	3826	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25722340	13413	0	0
T4	15956	181	0	0
T14	8814	0	0	0
T15	4615	0	0	0
T16	9963	0	0	0
T17	15434	0	0	0
T18	4010	0	0	0
T19	149500	0	0	0
T33	4022	0	0	0
T34	11075	0	0	0
T52	0	40	0	0
T62	0	466	0	0
T66	0	330	0	0
T70	0	70	0	0
T74	0	430	0	0
T103	1098	0	0	0
T105	0	330	0	0
T117	0	58	0	0
T118	0	62	0	0
T119	0	428	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25722340	3640	0	0
T5	3339	0	0	0
T20	3575	0	0	0
T37	3617	0	0	0
T49	0	44	0	0
T55	1857	0	0	0
T66	0	25	0	0
T70	0	60	0	0
T90	6627	0	0	0
T105	63086	61	0	0
T107	9974	0	0	0
T108	4700	0	0	0
T109	21467	0	0	0
T121	7482	0	0	0
T167	0	13	0	0
T168	0	75	0	0
T169	0	71	0	0
T170	0	41	0	0
T171	0	53	0	0
T172	0	11	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25722340	3796	0	0
T5	3339	0	0	0
T20	3575	0	0	0
T37	3617	0	0	0
T49	0	53	0	0
T55	1857	0	0	0
T66	0	20	0	0
T70	0	72	0	0
T90	6627	0	0	0
T105	63086	42	0	0
T107	9974	0	0	0
T108	4700	0	0	0
T109	21467	0	0	0
T121	7482	0	0	0
T167	0	14	0	0
T168	0	68	0	0
T169	0	77	0	0
T170	0	69	0	0
T171	0	31	0	0
T172	0	10	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25722340	3787	0	0
T5	3339	0	0	0
T20	3575	0	0	0
T37	3617	0	0	0
T49	0	17	0	0
T55	1857	0	0	0
T66	0	31	0	0
T70	0	65	0	0
T90	6627	0	0	0
T105	63086	42	0	0
T107	9974	0	0	0
T108	4700	0	0	0
T109	21467	0	0	0
T121	7482	0	0	0
T167	0	15	0	0
T168	0	71	0	0
T169	0	56	0	0
T170	0	57	0	0
T171	0	24	0	0
T172	0	5	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25722340	3795	0	0
T5	3339	0	0	0
T20	3575	0	0	0
T37	3617	0	0	0
T49	0	54	0	0
T55	1857	0	0	0
T66	0	39	0	0
T70	0	75	0	0
T90	6627	0	0	0
T105	63086	45	0	0
T107	9974	0	0	0
T108	4700	0	0	0
T109	21467	0	0	0
T121	7482	0	0	0
T167	0	16	0	0
T168	0	56	0	0
T169	0	83	0	0
T170	0	92	0	0
T171	0	42	0	0
T172	0	7	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25722340	3792	0	0
T5	3339	0	0	0
T20	3575	0	0	0
T37	3617	0	0	0
T49	0	36	0	0
T55	1857	0	0	0
T66	0	40	0	0
T70	0	85	0	0
T90	6627	0	0	0
T105	63086	61	0	0
T107	9974	0	0	0
T108	4700	0	0	0
T109	21467	0	0	0
T121	7482	0	0	0
T167	0	19	0	0
T168	0	56	0	0
T169	0	54	0	0
T170	0	56	0	0
T171	0	45	0	0
T173	0	5	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25722340	3795	0	0
T5	3339	0	0	0
T20	3575	0	0	0
T37	3617	0	0	0
T49	0	31	0	0
T55	1857	0	0	0
T66	0	39	0	0
T70	0	60	0	0
T90	6627	0	0	0
T105	63086	47	0	0
T107	9974	0	0	0
T108	4700	0	0	0
T109	21467	0	0	0
T121	7482	0	0	0
T167	0	9	0	0
T168	0	58	0	0
T169	0	63	0	0
T170	0	82	0	0
T171	0	30	0	0
T172	0	17	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25722340	3834	0	0
T5	3339	0	0	0
T20	3575	0	0	0
T37	3617	0	0	0
T49	0	61	0	0
T55	1857	0	0	0
T66	0	26	0	0
T70	0	67	0	0
T90	6627	0	0	0
T105	63086	74	0	0
T107	9974	0	0	0
T108	4700	0	0	0
T109	21467	0	0	0
T121	7482	0	0	0
T167	0	16	0	0
T168	0	38	0	0
T169	0	55	0	0
T170	0	86	0	0
T171	0	40	0	0
T172	0	11	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25722340	3850	0	0
T5	3339	0	0	0
T20	3575	0	0	0
T37	3617	0	0	0
T49	0	30	0	0
T55	1857	0	0	0
T66	0	40	0	0
T70	0	65	0	0
T90	6627	0	0	0
T105	63086	69	0	0
T107	9974	0	0	0
T108	4700	0	0	0
T109	21467	0	0	0
T121	7482	0	0	0
T167	0	21	0	0
T168	0	69	0	0
T169	0	41	0	0
T170	0	58	0	0
T171	0	50	0	0
T172	0	15	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25722340	4341	0	0
T5	3339	0	0	0
T7	0	29	0	0
T20	3575	0	0	0
T37	3617	0	0	0
T45	0	50	0	0
T55	1857	0	0	0
T66	0	50	0	0
T70	0	86	0	0
T90	6627	0	0	0
T105	63086	130	0	0
T107	9974	0	0	0
T108	4700	0	0	0
T109	21467	0	0	0
T121	7482	0	0	0
T167	0	35	0	0
T168	0	129	0	0
T169	0	117	0	0
T174	0	57	0	0
T175	0	9	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25722340	3517	0	0
T5	3339	0	0	0
T20	3575	0	0	0
T37	3617	0	0	0
T49	0	40	0	0
T55	1857	0	0	0
T66	0	31	0	0
T70	0	58	0	0
T90	6627	0	0	0
T105	63086	62	0	0
T107	9974	0	0	0
T108	4700	0	0	0
T109	21467	0	0	0
T121	7482	0	0	0
T167	0	10	0	0
T168	0	57	0	0
T169	0	64	0	0
T170	0	49	0	0
T171	0	38	0	0
T172	0	19	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25722340	3908	0	0
T5	3339	0	0	0
T20	3575	0	0	0
T37	3617	0	0	0
T49	0	61	0	0
T55	1857	0	0	0
T66	0	24	0	0
T70	0	70	0	0
T90	6627	0	0	0
T105	63086	59	0	0
T107	9974	0	0	0
T108	4700	0	0	0
T109	21467	0	0	0
T121	7482	0	0	0
T167	0	25	0	0
T168	0	94	0	0
T169	0	57	0	0
T170	0	94	0	0
T171	0	44	0	0
T172	0	23	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25722340	3541	0	0
T5	3339	0	0	0
T20	3575	0	0	0
T37	3617	0	0	0
T49	0	49	0	0
T55	1857	0	0	0
T66	0	39	0	0
T70	0	45	0	0
T90	6627	0	0	0
T105	63086	43	0	0
T107	9974	0	0	0
T108	4700	0	0	0
T109	21467	0	0	0
T121	7482	0	0	0
T167	0	4	0	0
T168	0	63	0	0
T169	0	70	0	0
T170	0	73	0	0
T171	0	31	0	0
T172	0	13	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25722340	3724	0	0
T5	3339	0	0	0
T20	3575	0	0	0
T37	3617	0	0	0
T49	0	33	0	0
T55	1857	0	0	0
T66	0	27	0	0
T70	0	43	0	0
T90	6627	0	0	0
T105	63086	70	0	0
T107	9974	0	0	0
T108	4700	0	0	0
T109	21467	0	0	0
T121	7482	0	0	0
T167	0	9	0	0
T168	0	56	0	0
T169	0	63	0	0
T170	0	74	0	0
T171	0	56	0	0
T172	0	14	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25722340	3901	0	0
T5	3339	0	0	0
T20	3575	0	0	0
T37	3617	0	0	0
T49	0	24	0	0
T55	1857	0	0	0
T66	0	29	0	0
T70	0	66	0	0
T90	6627	0	0	0
T105	63086	82	0	0
T107	9974	0	0	0
T108	4700	0	0	0
T109	21467	0	0	0
T121	7482	0	0	0
T167	0	14	0	0
T168	0	47	0	0
T169	0	49	0	0
T170	0	36	0	0
T171	0	46	0	0
T172	0	10	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25722340	3625	0	0
T5	3339	0	0	0
T20	3575	0	0	0
T37	3617	0	0	0
T49	0	60	0	0
T55	1857	0	0	0
T66	0	33	0	0
T70	0	53	0	0
T90	6627	0	0	0
T105	63086	59	0	0
T107	9974	0	0	0
T108	4700	0	0	0
T109	21467	0	0	0
T121	7482	0	0	0
T167	0	34	0	0
T168	0	32	0	0
T169	0	51	0	0
T170	0	60	0	0
T171	0	20	0	0
T172	0	16	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25722340	3752	0	0
T5	3339	0	0	0
T20	3575	0	0	0
T37	3617	0	0	0
T49	0	46	0	0
T55	1857	0	0	0
T66	0	30	0	0
T70	0	33	0	0
T90	6627	0	0	0
T105	63086	90	0	0
T107	9974	0	0	0
T108	4700	0	0	0
T109	21467	0	0	0
T121	7482	0	0	0
T167	0	10	0	0
T168	0	77	0	0
T169	0	68	0	0
T170	0	58	0	0
T171	0	19	0	0
T172	0	11	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25722340	3805	0	0
T5	3339	0	0	0
T20	3575	0	0	0
T37	3617	0	0	0
T49	0	34	0	0
T55	1857	0	0	0
T66	0	36	0	0
T70	0	64	0	0
T90	6627	0	0	0
T105	63086	39	0	0
T107	9974	0	0	0
T108	4700	0	0	0
T109	21467	0	0	0
T121	7482	0	0	0
T167	0	22	0	0
T168	0	49	0	0
T169	0	44	0	0
T170	0	77	0	0
T171	0	44	0	0
T172	0	16	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25722340	3754	0	0
T5	3339	0	0	0
T20	3575	0	0	0
T37	3617	0	0	0
T49	0	48	0	0
T55	1857	0	0	0
T66	0	25	0	0
T70	0	65	0	0
T90	6627	0	0	0
T105	63086	67	0	0
T107	9974	0	0	0
T108	4700	0	0	0
T109	21467	0	0	0
T121	7482	0	0	0
T167	0	11	0	0
T168	0	64	0	0
T169	0	51	0	0
T170	0	83	0	0
T171	0	26	0	0
T172	0	12	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25722340	3754	0	0
T5	3339	0	0	0
T20	3575	0	0	0
T37	3617	0	0	0
T49	0	53	0	0
T55	1857	0	0	0
T66	0	25	0	0
T70	0	76	0	0
T90	6627	0	0	0
T105	63086	39	0	0
T107	9974	0	0	0
T108	4700	0	0	0
T109	21467	0	0	0
T121	7482	0	0	0
T167	0	16	0	0
T168	0	86	0	0
T169	0	53	0	0
T170	0	48	0	0
T171	0	32	0	0
T176	0	8	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25722340	3920	0	0
T5	3339	0	0	0
T20	3575	0	0	0
T37	3617	0	0	0
T49	0	62	0	0
T55	1857	0	0	0
T66	0	32	0	0
T70	0	75	0	0
T90	6627	0	0	0
T105	63086	49	0	0
T107	9974	0	0	0
T108	4700	0	0	0
T109	21467	0	0	0
T121	7482	0	0	0
T167	0	16	0	0
T168	0	78	0	0
T169	0	44	0	0
T170	0	54	0	0
T171	0	14	0	0
T172	0	28	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25722340	3784	0	0
T5	3339	0	0	0
T20	3575	0	0	0
T37	3617	0	0	0
T49	0	38	0	0
T55	1857	0	0	0
T66	0	28	0	0
T70	0	46	0	0
T90	6627	0	0	0
T105	63086	64	0	0
T107	9974	0	0	0
T108	4700	0	0	0
T109	21467	0	0	0
T121	7482	0	0	0
T167	0	17	0	0
T168	0	62	0	0
T169	0	46	0	0
T170	0	45	0	0
T171	0	37	0	0
T172	0	9	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25722340	3636	0	0
T5	3339	0	0	0
T20	3575	0	0	0
T37	3617	0	0	0
T49	0	80	0	0
T55	1857	0	0	0
T66	0	24	0	0
T70	0	48	0	0
T90	6627	0	0	0
T105	63086	44	0	0
T107	9974	0	0	0
T108	4700	0	0	0
T109	21467	0	0	0
T121	7482	0	0	0
T167	0	4	0	0
T168	0	84	0	0
T169	0	83	0	0
T170	0	96	0	0
T171	0	36	0	0
T172	0	5	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25722340	3818	0	0
T5	3339	0	0	0
T20	3575	0	0	0
T37	3617	0	0	0
T49	0	58	0	0
T55	1857	0	0	0
T66	0	47	0	0
T70	0	67	0	0
T90	6627	0	0	0
T105	63086	65	0	0
T107	9974	0	0	0
T108	4700	0	0	0
T109	21467	0	0	0
T121	7482	0	0	0
T167	0	16	0	0
T168	0	34	0	0
T169	0	44	0	0
T170	0	52	0	0
T171	0	28	0	0
T172	0	7	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25722340	3713	0	0
T5	3339	0	0	0
T20	3575	0	0	0
T37	3617	0	0	0
T49	0	27	0	0
T55	1857	0	0	0
T66	0	15	0	0
T70	0	60	0	0
T90	6627	0	0	0
T105	63086	51	0	0
T107	9974	0	0	0
T108	4700	0	0	0
T109	21467	0	0	0
T121	7482	0	0	0
T167	0	9	0	0
T168	0	75	0	0
T169	0	70	0	0
T170	0	73	0	0
T171	0	28	0	0
T172	0	23	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25722340	3621	0	0
T5	3339	0	0	0
T20	3575	0	0	0
T37	3617	0	0	0
T49	0	65	0	0
T55	1857	0	0	0
T66	0	19	0	0
T70	0	42	0	0
T90	6627	0	0	0
T105	63086	50	0	0
T107	9974	0	0	0
T108	4700	0	0	0
T109	21467	0	0	0
T121	7482	0	0	0
T167	0	13	0	0
T168	0	39	0	0
T169	0	70	0	0
T170	0	61	0	0
T171	0	39	0	0
T172	0	26	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25722340	3806	0	0
T5	3339	0	0	0
T20	3575	0	0	0
T37	3617	0	0	0
T49	0	57	0	0
T55	1857	0	0	0
T66	0	56	0	0
T70	0	38	0	0
T90	6627	0	0	0
T105	63086	38	0	0
T107	9974	0	0	0
T108	4700	0	0	0
T109	21467	0	0	0
T121	7482	0	0	0
T167	0	21	0	0
T168	0	96	0	0
T169	0	48	0	0
T170	0	65	0	0
T171	0	21	0	0
T172	0	18	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25722340	3810	0	0
T5	3339	0	0	0
T20	3575	0	0	0
T37	3617	0	0	0
T49	0	53	0	0
T55	1857	0	0	0
T66	0	12	0	0
T70	0	69	0	0
T90	6627	0	0	0
T105	63086	46	0	0
T107	9974	0	0	0
T108	4700	0	0	0
T109	21467	0	0	0
T121	7482	0	0	0
T167	0	12	0	0
T168	0	53	0	0
T169	0	56	0	0
T170	0	78	0	0
T171	0	40	0	0
T172	0	13	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25722340	3750	0	0
T5	3339	0	0	0
T20	3575	0	0	0
T37	3617	0	0	0
T49	0	50	0	0
T55	1857	0	0	0
T66	0	44	0	0
T70	0	80	0	0
T90	6627	0	0	0
T105	63086	51	0	0
T107	9974	0	0	0
T108	4700	0	0	0
T109	21467	0	0	0
T121	7482	0	0	0
T167	0	18	0	0
T168	0	72	0	0
T169	0	71	0	0
T170	0	74	0	0
T171	0	41	0	0
T172	0	15	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25722340	3590	0	0
T5	3339	0	0	0
T20	3575	0	0	0
T37	3617	0	0	0
T49	0	58	0	0
T55	1857	0	0	0
T66	0	19	0	0
T70	0	53	0	0
T90	6627	0	0	0
T105	63086	51	0	0
T107	9974	0	0	0
T108	4700	0	0	0
T109	21467	0	0	0
T121	7482	0	0	0
T167	0	7	0	0
T168	0	64	0	0
T169	0	72	0	0
T170	0	59	0	0
T171	0	29	0	0
T172	0	8	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25722340	3716	0	0
T5	3339	0	0	0
T20	3575	0	0	0
T37	3617	0	0	0
T49	0	64	0	0
T55	1857	0	0	0
T66	0	40	0	0
T70	0	56	0	0
T90	6627	0	0	0
T105	63086	40	0	0
T107	9974	0	0	0
T108	4700	0	0	0
T109	21467	0	0	0
T121	7482	0	0	0
T167	0	21	0	0
T168	0	84	0	0
T169	0	54	0	0
T170	0	79	0	0
T171	0	18	0	0
T172	0	11	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25722340	3826	0	0
T5	3339	0	0	0
T20	3575	0	0	0
T37	3617	0	0	0
T49	0	28	0	0
T55	1857	0	0	0
T66	0	41	0	0
T70	0	68	0	0
T90	6627	0	0	0
T105	63086	54	0	0
T107	9974	0	0	0
T108	4700	0	0	0
T109	21467	0	0	0
T121	7482	0	0	0
T167	0	26	0	0
T168	0	59	0	0
T169	0	40	0	0
T170	0	35	0	0
T171	0	37	0	0
T172	0	16	0	0