Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3167122	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

611092

1

T1

144

T2

273

T3

393

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3362776	1			T1	338		T2	2528		T3	940
values[0x0]	205269	1			T1	40		T2	67		T3	163
values[0x1]	210169	1			T1	41		T2	70		T3	157

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2170004	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1608210

1

T1

195

T2

1043

T3

649

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	13499	1			T3	1260		T4	6		T15	5
valid_sources[0x01]	16570	1			T4	7		T15	5		T16	41
valid_sources[0x02]	13007	1			T4	7		T15	4		T18	17
valid_sources[0x03]	13168	1			T4	6		T15	1		T18	28
valid_sources[0x04]	12351	1			T4	3		T15	7		T18	52
valid_sources[0x05]	20036	1			T4	4		T15	4		T18	36
valid_sources[0x06]	13244	1			T4	1		T15	6		T18	15
valid_sources[0x07]	21172	1			T4	9		T15	9		T18	38
valid_sources[0x08]	12011	1			T4	1		T15	4		T18	7
valid_sources[0x09]	12601	1			T4	5		T15	11		T18	1
valid_sources[0x0a]	16848	1			T4	7		T15	5		T18	20
valid_sources[0x0b]	26039	1			T4	4		T15	7		T18	17
valid_sources[0x0c]	13673	1			T4	3		T15	7		T18	10
valid_sources[0x0d]	16986	1			T4	4		T15	9		T18	34
valid_sources[0x0e]	12646	1			T4	3		T15	12		T18	4
valid_sources[0x0f]	13810	1			T4	2		T15	1		T18	33
valid_sources[0x10]	13045	1			T4	2		T15	6		T18	4
valid_sources[0x11]	13268	1			T4	4		T15	9		T18	28
valid_sources[0x12]	13168	1			T4	2		T15	5		T18	10
valid_sources[0x13]	12858	1			T4	3		T15	4		T18	1
valid_sources[0x14]	12465	1			T4	1		T15	8		T18	59
valid_sources[0x15]	13262	1			T4	6		T15	4		T18	7
valid_sources[0x16]	14244	1			T4	3		T15	9		T18	8
valid_sources[0x17]	14309	1			T4	5		T15	5		T18	26
valid_sources[0x18]	13411	1			T4	3		T15	1		T16	1
valid_sources[0x19]	14662	1			T4	2		T15	5		T18	18
valid_sources[0x1a]	15367	1			T4	2		T15	5		T18	45
valid_sources[0x1b]	12690	1			T4	3		T15	4		T18	36
valid_sources[0x1c]	14574	1			T4	3		T15	4		T18	27
valid_sources[0x1d]	16243	1			T4	4		T15	7		T18	18
valid_sources[0x1e]	12716	1			T4	3		T15	8		T18	31
valid_sources[0x1f]	13322	1			T4	3		T15	9		T18	4
valid_sources[0x20]	12023	1			T4	6		T15	3		T18	30
valid_sources[0x21]	12251	1			T4	2		T15	10		T18	13
valid_sources[0x22]	15215	1			T4	5		T15	4		T18	34
valid_sources[0x23]	12847	1			T4	8		T15	4		T18	27
valid_sources[0x24]	12071	1			T4	2		T15	7		T18	26
valid_sources[0x25]	25680	1			T4	2		T15	6		T18	27
valid_sources[0x26]	13435	1			T4	4		T15	7		T18	46
valid_sources[0x27]	12254	1			T4	6		T15	3		T16	2
valid_sources[0x28]	12925	1			T4	3		T15	6		T18	26
valid_sources[0x29]	14170	1			T4	6		T15	2		T18	24
valid_sources[0x2a]	19431	1			T4	6		T15	6		T18	22
valid_sources[0x2b]	24720	1			T4	5		T15	9		T18	16
valid_sources[0x2c]	12253	1			T4	2		T15	3		T16	1
valid_sources[0x2d]	13185	1			T4	1		T15	5		T18	37
valid_sources[0x2e]	12482	1			T4	3		T15	5		T16	1
valid_sources[0x2f]	19044	1			T4	3		T15	4		T18	34
valid_sources[0x30]	15973	1			T2	2665		T4	4		T15	5
valid_sources[0x31]	14705	1			T4	7		T15	4		T18	3
valid_sources[0x32]	13623	1			T1	419		T4	4		T15	7
valid_sources[0x33]	16333	1			T4	4		T15	5		T18	15
valid_sources[0x34]	11936	1			T4	4		T15	5		T18	35
valid_sources[0x35]	12227	1			T4	5		T15	4		T18	12
valid_sources[0x36]	12617	1			T4	3		T18	18		T19	2
valid_sources[0x37]	13104	1			T4	1		T15	5		T16	57
valid_sources[0x38]	12360	1			T4	4		T15	6		T16	1
valid_sources[0x39]	12586	1			T4	3		T15	7		T18	26
valid_sources[0x3a]	13282	1			T4	3		T15	4		T18	38
valid_sources[0x3b]	16263	1			T4	2		T15	3		T18	33
valid_sources[0x3c]	14162	1			T4	5		T15	4		T18	34
valid_sources[0x3d]	12403	1			T4	3		T15	8		T16	1
valid_sources[0x3e]	15704	1			T4	5		T18	34		T23	4
valid_sources[0x3f]	23765	1			T4	5		T15	5		T18	33
valid_sources[0x40]	12315	1			T4	3		T15	6		T18	19
valid_sources[0x41]	13198	1			T4	1		T15	7		T18	17
valid_sources[0x42]	12524	1			T4	6		T15	4		T19	2
valid_sources[0x43]	12187	1			T4	4		T15	6		T18	25
valid_sources[0x44]	13607	1			T4	1		T15	2		T18	33
valid_sources[0x45]	12882	1			T4	6		T15	6		T18	28
valid_sources[0x46]	12836	1			T4	7		T15	6		T18	21
valid_sources[0x47]	15814	1			T4	4		T15	8		T18	57
valid_sources[0x48]	12984	1			T4	3		T15	7		T18	41
valid_sources[0x49]	17851	1			T4	6		T15	1		T18	5
valid_sources[0x4a]	12838	1			T4	3		T15	9		T18	56
valid_sources[0x4b]	13185	1			T4	6		T15	5		T18	22
valid_sources[0x4c]	13288	1			T4	5		T15	6		T18	54
valid_sources[0x4d]	15469	1			T4	3		T15	6		T18	18
valid_sources[0x4e]	34677	1			T4	3		T15	1		T18	17
valid_sources[0x4f]	12218	1			T4	3		T15	7		T18	34
valid_sources[0x50]	13020	1			T4	5		T15	6		T18	12
valid_sources[0x51]	12635	1			T4	2		T15	10		T16	2
valid_sources[0x52]	16207	1			T4	3		T15	1		T18	50
valid_sources[0x53]	11777	1			T4	3		T15	10		T18	67
valid_sources[0x54]	12230	1			T4	2		T15	11		T16	145
valid_sources[0x55]	13241	1			T4	3		T15	10		T16	4
valid_sources[0x56]	12475	1			T4	5		T15	7		T19	1
valid_sources[0x57]	14000	1			T4	7		T15	2		T18	10
valid_sources[0x58]	12045	1			T4	10		T15	13		T18	14
valid_sources[0x59]	13395	1			T4	7		T15	6		T18	49
valid_sources[0x5a]	13381	1			T4	1		T15	2		T18	20
valid_sources[0x5b]	14277	1			T4	2		T15	7		T18	52
valid_sources[0x5c]	14072	1			T4	4		T15	4		T18	28
valid_sources[0x5d]	12124	1			T4	5		T15	6		T16	1
valid_sources[0x5e]	12435	1			T4	8		T15	5		T18	4
valid_sources[0x5f]	15338	1			T4	6		T15	5		T18	37
valid_sources[0x60]	13181	1			T4	3		T15	5		T16	10
valid_sources[0x61]	13421	1			T4	6		T15	6		T18	64
valid_sources[0x62]	12703	1			T4	3		T15	10		T18	25
valid_sources[0x63]	14157	1			T4	4		T15	8		T18	34
valid_sources[0x64]	12230	1			T4	2		T15	6		T18	5
valid_sources[0x65]	13366	1			T4	3		T15	4		T16	1
valid_sources[0x66]	12408	1			T4	7		T15	5		T16	1
valid_sources[0x67]	12509	1			T4	2		T15	3		T18	12
valid_sources[0x68]	11842	1			T4	7		T15	3		T18	24
valid_sources[0x69]	13210	1			T4	1		T15	8		T18	21
valid_sources[0x6a]	12112	1			T4	3		T15	5		T18	3
valid_sources[0x6b]	16079	1			T4	1		T15	7		T18	12
valid_sources[0x6c]	18653	1			T4	3		T15	4		T17	1343
valid_sources[0x6d]	13995	1			T4	3		T15	2		T18	18
valid_sources[0x6e]	13141	1			T4	6		T15	4		T18	39
valid_sources[0x6f]	13870	1			T4	6		T15	5		T16	1
valid_sources[0x70]	12885	1			T4	2		T15	6		T18	7
valid_sources[0x71]	13697	1			T4	3		T15	2		T18	20
valid_sources[0x72]	13826	1			T4	3		T15	3		T18	50
valid_sources[0x73]	13000	1			T4	2		T15	1		T18	15
valid_sources[0x74]	23765	1			T4	3		T15	6		T18	36
valid_sources[0x75]	17276	1			T4	2		T14	2888		T15	6
valid_sources[0x76]	12469	1			T4	5		T15	5		T18	23
valid_sources[0x77]	13488	1			T4	5		T15	11		T18	52
valid_sources[0x78]	12147	1			T4	3		T15	5		T18	28
valid_sources[0x79]	15835	1			T4	9		T15	6		T18	23
valid_sources[0x7a]	12411	1			T4	3		T15	6		T18	24
valid_sources[0x7b]	52618	1			T4	7		T15	6		T18	27
valid_sources[0x7c]	13475	1			T4	4		T15	6		T18	37
valid_sources[0x7d]	14628	1			T4	6		T15	3		T18	9
valid_sources[0x7e]	17138	1			T4	2		T15	12		T18	35
valid_sources[0x7f]	12788	1			T4	6		T15	6		T16	2
valid_sources[0x80]	13947	1			T4	6		T15	1		T18	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

331090

1

T1

119

T2

226

T3

159

values[0x0]

all_enables

biggest_size

146788

1

T1

14

T2

29

T3

123

values[0x1]

all_enables

biggest_size

133214

1

T1

11

T2

18

T3

111