Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2824889	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

610638

1

T1

413

T2

150

T3

144

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3028545	1			T1	692		T2	404		T3	698
values[0x0]	202572	1			T1	154		T2	47		T3	41
values[0x1]	204410	1			T1	131		T2	41		T3	39

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1943524	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1492003

1

T1

542

T2

238

T3

333

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	35278	1			T3	7		T15	7		T16	27
valid_sources[0x01]	10206	1			T2	5		T15	3		T16	25
valid_sources[0x02]	10915	1			T2	1		T15	6		T16	29
valid_sources[0x03]	18280	1			T3	2		T5	10		T15	10
valid_sources[0x04]	10424	1			T2	1		T3	1		T5	1
valid_sources[0x05]	10289	1			T2	2		T3	3		T5	1
valid_sources[0x06]	9811	1			T5	2		T15	2		T16	32
valid_sources[0x07]	11577	1			T2	2		T3	6		T15	8
valid_sources[0x08]	9805	1			T3	4		T15	3		T16	37
valid_sources[0x09]	8487	1			T2	1		T3	3		T15	5
valid_sources[0x0a]	11935	1			T2	3		T3	3		T15	2
valid_sources[0x0b]	10091	1			T3	5		T15	1		T16	46
valid_sources[0x0c]	10134	1			T2	1		T5	2		T15	9
valid_sources[0x0d]	45122	1			T2	1		T3	2		T15	3
valid_sources[0x0e]	12780	1			T3	9		T5	3		T15	3
valid_sources[0x0f]	10459	1			T2	2		T5	7		T16	29
valid_sources[0x10]	17828	1			T2	2		T3	6		T5	2
valid_sources[0x11]	11148	1			T2	1		T3	10		T5	8
valid_sources[0x12]	10349	1			T3	1		T15	7		T16	22
valid_sources[0x13]	10301	1			T2	4		T3	1		T5	1
valid_sources[0x14]	9385	1			T3	1		T5	13		T15	8
valid_sources[0x15]	13188	1			T3	1		T15	11		T16	26
valid_sources[0x16]	10376	1			T15	5		T16	26		T17	1
valid_sources[0x17]	9627	1			T2	1		T15	1		T16	23
valid_sources[0x18]	10173	1			T3	4		T5	1		T15	2
valid_sources[0x19]	16200	1			T2	2		T3	3		T15	1
valid_sources[0x1a]	13878	1			T2	3		T3	1		T15	8
valid_sources[0x1b]	17683	1			T15	3		T16	26		T17	1
valid_sources[0x1c]	10355	1			T15	2		T16	23		T26	2
valid_sources[0x1d]	10178	1			T2	2		T3	8		T5	4
valid_sources[0x1e]	9197	1			T2	5		T15	5		T16	31
valid_sources[0x1f]	10981	1			T2	3		T3	2		T15	5
valid_sources[0x20]	14495	1			T2	3		T3	5		T15	10
valid_sources[0x21]	10767	1			T2	4		T3	5		T15	13
valid_sources[0x22]	11234	1			T2	6		T3	3		T15	7
valid_sources[0x23]	10953	1			T3	6		T15	4		T16	25
valid_sources[0x24]	12242	1			T2	1		T3	3		T5	5
valid_sources[0x25]	11002	1			T15	1		T16	28		T17	5
valid_sources[0x26]	16929	1			T2	5		T3	2		T16	24
valid_sources[0x27]	10447	1			T2	1		T3	4		T15	4
valid_sources[0x28]	11213	1			T3	3		T15	13		T16	31
valid_sources[0x29]	9915	1			T2	2		T16	23		T19	48
valid_sources[0x2a]	10182	1			T3	5		T15	2		T16	23
valid_sources[0x2b]	10374	1			T2	4		T3	1		T15	6
valid_sources[0x2c]	40427	1			T2	3		T3	2		T4	2256
valid_sources[0x2d]	10248	1			T2	3		T3	5		T5	3
valid_sources[0x2e]	39567	1			T5	9		T15	12		T16	34
valid_sources[0x2f]	9414	1			T2	1		T3	4		T5	3
valid_sources[0x30]	11408	1			T16	28		T17	6		T43	51
valid_sources[0x31]	20524	1			T2	3		T3	4		T15	4
valid_sources[0x32]	11128	1			T2	4		T3	3		T15	1
valid_sources[0x33]	9356	1			T2	1		T3	6		T15	7
valid_sources[0x34]	10200	1			T2	4		T3	4		T15	4
valid_sources[0x35]	10419	1			T3	4		T5	12		T15	6
valid_sources[0x36]	9991	1			T2	8		T3	3		T5	2
valid_sources[0x37]	10849	1			T2	4		T3	2		T15	4
valid_sources[0x38]	10252	1			T2	4		T3	11		T5	5
valid_sources[0x39]	18023	1			T2	7		T3	2		T15	12
valid_sources[0x3a]	11659	1			T15	3		T16	29		T17	3
valid_sources[0x3b]	12450	1			T3	1		T15	4		T16	23
valid_sources[0x3c]	12255	1			T2	1		T3	5		T15	1
valid_sources[0x3d]	10598	1			T2	2		T5	2		T15	5
valid_sources[0x3e]	14454	1			T2	4		T3	1		T15	2
valid_sources[0x3f]	10143	1			T3	4		T5	1		T15	7
valid_sources[0x40]	10697	1			T3	1		T15	1		T16	28
valid_sources[0x41]	32685	1			T2	3		T3	5		T5	17
valid_sources[0x42]	10119	1			T2	1		T5	6		T15	3
valid_sources[0x43]	13294	1			T2	1		T3	2		T15	2
valid_sources[0x44]	11823	1			T3	4		T5	4		T15	1
valid_sources[0x45]	13228	1			T15	5		T16	29		T17	2
valid_sources[0x46]	9852	1			T2	2		T3	1		T16	28
valid_sources[0x47]	13601	1			T2	3		T5	4		T15	2
valid_sources[0x48]	9178	1			T2	1		T5	4		T15	7
valid_sources[0x49]	32948	1			T2	1		T3	3		T15	6
valid_sources[0x4a]	11915	1			T2	8		T3	6		T15	2
valid_sources[0x4b]	18661	1			T2	1		T16	19		T17	1
valid_sources[0x4c]	10061	1			T3	6		T15	11		T16	33
valid_sources[0x4d]	11285	1			T2	3		T15	8		T16	29
valid_sources[0x4e]	17420	1			T2	3		T3	1		T15	3
valid_sources[0x4f]	9601	1			T2	1		T5	1		T15	3
valid_sources[0x50]	37956	1			T3	8		T5	4		T15	1
valid_sources[0x51]	9629	1			T15	16		T16	21		T17	2
valid_sources[0x52]	9583	1			T2	1		T3	5		T15	1
valid_sources[0x53]	14451	1			T2	3		T15	4		T16	27
valid_sources[0x54]	10446	1			T2	1		T5	9		T15	5
valid_sources[0x55]	9293	1			T2	1		T3	10		T15	4
valid_sources[0x56]	10330	1			T5	3		T15	7		T16	20
valid_sources[0x57]	15413	1			T2	2		T3	10		T15	4
valid_sources[0x58]	9652	1			T2	1		T3	2		T15	3
valid_sources[0x59]	11642	1			T2	2		T15	3		T16	22
valid_sources[0x5a]	18051	1			T3	4		T15	6		T16	27
valid_sources[0x5b]	9971	1			T5	9		T15	4		T16	37
valid_sources[0x5c]	16553	1			T1	977		T2	10		T3	2
valid_sources[0x5d]	10152	1			T3	4		T15	3		T16	34
valid_sources[0x5e]	18907	1			T3	5		T5	5		T15	3
valid_sources[0x5f]	9682	1			T2	2		T3	5		T5	1
valid_sources[0x60]	11134	1			T2	7		T15	4		T16	36
valid_sources[0x61]	11347	1			T3	1		T5	1		T15	6
valid_sources[0x62]	10359	1			T2	2		T3	1		T16	26
valid_sources[0x63]	10513	1			T3	5		T15	10		T16	39
valid_sources[0x64]	42841	1			T2	3		T3	4		T5	3
valid_sources[0x65]	9971	1			T2	3		T3	3		T16	31
valid_sources[0x66]	10941	1			T2	4		T3	2		T15	7
valid_sources[0x67]	9302	1			T15	1		T16	29		T17	1
valid_sources[0x68]	15545	1			T2	3		T3	4		T5	1
valid_sources[0x69]	12736	1			T3	7		T15	11		T16	30
valid_sources[0x6a]	9538	1			T2	6		T3	4		T15	7
valid_sources[0x6b]	12286	1			T2	2		T3	6		T5	4
valid_sources[0x6c]	9513	1			T2	3		T3	1		T15	7
valid_sources[0x6d]	8982	1			T3	4		T5	4		T15	6
valid_sources[0x6e]	12744	1			T2	1		T3	7		T5	4
valid_sources[0x6f]	10447	1			T2	3		T3	8		T5	11
valid_sources[0x70]	13224	1			T2	3		T3	2		T5	7
valid_sources[0x71]	9403	1			T3	7		T5	9		T15	11
valid_sources[0x72]	12914	1			T2	1		T15	9		T16	29
valid_sources[0x73]	12961	1			T3	5		T5	7		T15	5
valid_sources[0x74]	10849	1			T3	6		T15	4		T16	31
valid_sources[0x75]	13272	1			T15	3		T16	24		T17	2
valid_sources[0x76]	50345	1			T2	2		T3	8		T15	2
valid_sources[0x77]	11893	1			T2	3		T3	1		T15	4
valid_sources[0x78]	9846	1			T3	1		T15	10		T16	37
valid_sources[0x79]	9385	1			T2	1		T3	2		T5	11
valid_sources[0x7a]	11683	1			T15	3		T16	30		T17	1
valid_sources[0x7b]	9585	1			T2	2		T3	1		T5	3
valid_sources[0x7c]	9541	1			T3	2		T5	3		T15	6
valid_sources[0x7d]	9966	1			T2	2		T3	2		T15	2
valid_sources[0x7e]	10509	1			T2	3		T3	6		T15	1
valid_sources[0x7f]	73663	1			T3	5		T5	1		T15	3
valid_sources[0x80]	11202	1			T3	5		T5	4		T15	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

335163

1

T1

250

T2

125

T3

126

values[0x0]

all_enables

biggest_size

145369

1

T1

88

T2

18

T3

14

values[0x1]

all_enables

biggest_size

130106

1

T1

75

T2

7

T3

4