Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	21268967	14414	0	0
attest_sw_binding_0_rd_A	21268967	3177	0	0
attest_sw_binding_1_rd_A	21268967	3327	0	0
attest_sw_binding_2_rd_A	21268967	2931	0	0
attest_sw_binding_3_rd_A	21268967	3080	0	0
attest_sw_binding_4_rd_A	21268967	3192	0	0
attest_sw_binding_5_rd_A	21268967	3197	0	0
attest_sw_binding_6_rd_A	21268967	3060	0	0
attest_sw_binding_7_rd_A	21268967	3233	0	0
intr_enable_rd_A	21268967	3911	0	0
key_version_rd_A	21268967	3101	0	0
max_creator_key_ver_regwen_rd_A	21268967	3331	0	0
max_owner_int_key_ver_regwen_rd_A	21268967	3310	0	0
max_owner_key_ver_regwen_rd_A	21268967	3255	0	0
reseed_interval_regwen_rd_A	21268967	3068	0	0
salt_0_rd_A	21268967	3100	0	0
salt_1_rd_A	21268967	3015	0	0
salt_2_rd_A	21268967	3156	0	0
salt_3_rd_A	21268967	3069	0	0
salt_4_rd_A	21268967	3236	0	0
salt_5_rd_A	21268967	3190	0	0
salt_6_rd_A	21268967	3125	0	0
salt_7_rd_A	21268967	3207	0	0
sealing_sw_binding_0_rd_A	21268967	3145	0	0
sealing_sw_binding_1_rd_A	21268967	3025	0	0
sealing_sw_binding_2_rd_A	21268967	3112	0	0
sealing_sw_binding_3_rd_A	21268967	3217	0	0
sealing_sw_binding_4_rd_A	21268967	3365	0	0
sealing_sw_binding_5_rd_A	21268967	3281	0	0
sealing_sw_binding_6_rd_A	21268967	3143	0	0
sealing_sw_binding_7_rd_A	21268967	3300	0	0
sideload_clear_rd_A	21268967	3099	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21268967	14414	0	0
T36	22474	0	0	0
T42	11943	261	0	0
T44	71957	0	0	0
T62	0	727	0	0
T74	0	462	0	0
T108	0	495	0	0
T113	8385	0	0	0
T119	0	567	0	0
T120	0	64	0	0
T121	0	781	0	0
T122	0	236	0	0
T123	0	50	0	0
T124	0	876	0	0
T125	4474	0	0	0
T126	62699	0	0	0
T127	5062	0	0	0
T128	10807	0	0	0
T129	10047	0	0	0
T130	15755	0	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21268967	3177	0	0
T120	50944	60	0	0
T121	30289	0	0	0
T122	22442	0	0	0
T123	0	23	0	0
T151	0	76	0	0
T156	0	10	0	0
T172	0	56	0	0
T173	0	23	0	0
T174	0	57	0	0
T175	0	44	0	0
T176	0	49	0	0
T177	0	107	0	0
T178	6516	0	0	0
T179	12454	0	0	0
T180	5117	0	0	0
T181	7566	0	0	0
T182	7481	0	0	0
T183	10221	0	0	0
T184	5338	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21268967	3327	0	0
T120	50944	67	0	0
T121	30289	0	0	0
T122	22442	0	0	0
T123	0	7	0	0
T151	0	103	0	0
T156	0	7	0	0
T172	0	65	0	0
T173	0	35	0	0
T174	0	58	0	0
T175	0	32	0	0
T176	0	43	0	0
T177	0	86	0	0
T178	6516	0	0	0
T179	12454	0	0	0
T180	5117	0	0	0
T181	7566	0	0	0
T182	7481	0	0	0
T183	10221	0	0	0
T184	5338	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21268967	2931	0	0
T120	50944	54	0	0
T121	30289	0	0	0
T122	22442	0	0	0
T123	0	17	0	0
T151	0	82	0	0
T156	0	8	0	0
T172	0	76	0	0
T173	0	26	0	0
T174	0	60	0	0
T175	0	27	0	0
T176	0	46	0	0
T177	0	63	0	0
T178	6516	0	0	0
T179	12454	0	0	0
T180	5117	0	0	0
T181	7566	0	0	0
T182	7481	0	0	0
T183	10221	0	0	0
T184	5338	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21268967	3080	0	0
T120	50944	91	0	0
T121	30289	0	0	0
T122	22442	0	0	0
T123	0	27	0	0
T151	0	58	0	0
T156	0	13	0	0
T172	0	53	0	0
T173	0	17	0	0
T174	0	35	0	0
T175	0	26	0	0
T176	0	76	0	0
T177	0	74	0	0
T178	6516	0	0	0
T179	12454	0	0	0
T180	5117	0	0	0
T181	7566	0	0	0
T182	7481	0	0	0
T183	10221	0	0	0
T184	5338	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21268967	3192	0	0
T120	50944	33	0	0
T121	30289	0	0	0
T122	22442	0	0	0
T123	0	28	0	0
T151	0	65	0	0
T156	0	14	0	0
T172	0	63	0	0
T173	0	35	0	0
T174	0	77	0	0
T175	0	22	0	0
T176	0	34	0	0
T177	0	63	0	0
T178	6516	0	0	0
T179	12454	0	0	0
T180	5117	0	0	0
T181	7566	0	0	0
T182	7481	0	0	0
T183	10221	0	0	0
T184	5338	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21268967	3197	0	0
T120	50944	60	0	0
T121	30289	0	0	0
T122	22442	0	0	0
T123	0	6	0	0
T151	0	80	0	0
T156	0	2	0	0
T172	0	59	0	0
T173	0	20	0	0
T174	0	54	0	0
T175	0	25	0	0
T176	0	40	0	0
T177	0	62	0	0
T178	6516	0	0	0
T179	12454	0	0	0
T180	5117	0	0	0
T181	7566	0	0	0
T182	7481	0	0	0
T183	10221	0	0	0
T184	5338	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21268967	3060	0	0
T120	50944	81	0	0
T121	30289	0	0	0
T122	22442	0	0	0
T123	0	5	0	0
T151	0	63	0	0
T156	0	13	0	0
T172	0	47	0	0
T173	0	34	0	0
T174	0	21	0	0
T175	0	39	0	0
T176	0	45	0	0
T177	0	43	0	0
T178	6516	0	0	0
T179	12454	0	0	0
T180	5117	0	0	0
T181	7566	0	0	0
T182	7481	0	0	0
T183	10221	0	0	0
T184	5338	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21268967	3233	0	0
T120	50944	52	0	0
T121	30289	0	0	0
T122	22442	0	0	0
T123	0	16	0	0
T151	0	78	0	0
T156	0	4	0	0
T172	0	74	0	0
T173	0	36	0	0
T174	0	73	0	0
T175	0	20	0	0
T176	0	32	0	0
T177	0	77	0	0
T178	6516	0	0	0
T179	12454	0	0	0
T180	5117	0	0	0
T181	7566	0	0	0
T182	7481	0	0	0
T183	10221	0	0	0
T184	5338	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21268967	3911	0	0
T30	4798	0	0	0
T42	11943	0	0	0
T43	188630	14	0	0
T44	71957	0	0	0
T47	4303	0	0	0
T67	0	33	0	0
T102	0	17	0	0
T120	0	54	0	0
T123	0	27	0	0
T133	27238	0	0	0
T134	8030	0	0	0
T172	0	48	0	0
T173	0	54	0	0
T185	0	56	0	0
T186	0	36	0	0
T187	0	27	0	0
T188	4898	0	0	0
T189	7889	0	0	0
T190	10038	0	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21268967	3101	0	0
T120	50944	58	0	0
T121	30289	0	0	0
T122	22442	0	0	0
T123	0	26	0	0
T151	0	85	0	0
T156	0	11	0	0
T172	0	53	0	0
T173	0	19	0	0
T174	0	45	0	0
T175	0	15	0	0
T176	0	45	0	0
T177	0	46	0	0
T178	6516	0	0	0
T179	12454	0	0	0
T180	5117	0	0	0
T181	7566	0	0	0
T182	7481	0	0	0
T183	10221	0	0	0
T184	5338	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21268967	3331	0	0
T120	50944	51	0	0
T121	30289	0	0	0
T122	22442	0	0	0
T123	0	30	0	0
T151	0	90	0	0
T156	0	10	0	0
T172	0	52	0	0
T173	0	27	0	0
T174	0	64	0	0
T175	0	36	0	0
T176	0	63	0	0
T177	0	86	0	0
T178	6516	0	0	0
T179	12454	0	0	0
T180	5117	0	0	0
T181	7566	0	0	0
T182	7481	0	0	0
T183	10221	0	0	0
T184	5338	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21268967	3310	0	0
T120	50944	48	0	0
T121	30289	0	0	0
T122	22442	0	0	0
T123	0	16	0	0
T151	0	79	0	0
T156	0	12	0	0
T172	0	65	0	0
T173	0	22	0	0
T174	0	65	0	0
T175	0	24	0	0
T176	0	52	0	0
T177	0	49	0	0
T178	6516	0	0	0
T179	12454	0	0	0
T180	5117	0	0	0
T181	7566	0	0	0
T182	7481	0	0	0
T183	10221	0	0	0
T184	5338	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21268967	3255	0	0
T120	50944	46	0	0
T121	30289	0	0	0
T122	22442	0	0	0
T123	0	20	0	0
T151	0	89	0	0
T156	0	10	0	0
T172	0	57	0	0
T173	0	32	0	0
T174	0	64	0	0
T175	0	32	0	0
T176	0	51	0	0
T177	0	65	0	0
T178	6516	0	0	0
T179	12454	0	0	0
T180	5117	0	0	0
T181	7566	0	0	0
T182	7481	0	0	0
T183	10221	0	0	0
T184	5338	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21268967	3068	0	0
T120	50944	56	0	0
T121	30289	0	0	0
T122	22442	0	0	0
T123	0	9	0	0
T151	0	93	0	0
T156	0	12	0	0
T172	0	59	0	0
T173	0	23	0	0
T174	0	88	0	0
T175	0	16	0	0
T176	0	68	0	0
T177	0	53	0	0
T178	6516	0	0	0
T179	12454	0	0	0
T180	5117	0	0	0
T181	7566	0	0	0
T182	7481	0	0	0
T183	10221	0	0	0
T184	5338	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21268967	3100	0	0
T120	50944	57	0	0
T121	30289	0	0	0
T122	22442	0	0	0
T123	0	6	0	0
T151	0	76	0	0
T156	0	2	0	0
T172	0	40	0	0
T173	0	47	0	0
T174	0	44	0	0
T175	0	30	0	0
T176	0	46	0	0
T177	0	55	0	0
T178	6516	0	0	0
T179	12454	0	0	0
T180	5117	0	0	0
T181	7566	0	0	0
T182	7481	0	0	0
T183	10221	0	0	0
T184	5338	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21268967	3015	0	0
T120	50944	44	0	0
T121	30289	0	0	0
T122	22442	0	0	0
T151	0	87	0	0
T156	0	6	0	0
T172	0	48	0	0
T173	0	30	0	0
T174	0	45	0	0
T175	0	35	0	0
T176	0	60	0	0
T177	0	37	0	0
T178	6516	0	0	0
T179	12454	0	0	0
T180	5117	0	0	0
T181	7566	0	0	0
T182	7481	0	0	0
T183	10221	0	0	0
T184	5338	0	0	0
T191	0	8	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21268967	3156	0	0
T120	50944	55	0	0
T121	30289	0	0	0
T122	22442	0	0	0
T123	0	14	0	0
T151	0	80	0	0
T156	0	24	0	0
T172	0	47	0	0
T173	0	30	0	0
T174	0	40	0	0
T175	0	27	0	0
T176	0	62	0	0
T177	0	65	0	0
T178	6516	0	0	0
T179	12454	0	0	0
T180	5117	0	0	0
T181	7566	0	0	0
T182	7481	0	0	0
T183	10221	0	0	0
T184	5338	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21268967	3069	0	0
T120	50944	43	0	0
T121	30289	0	0	0
T122	22442	0	0	0
T123	0	24	0	0
T151	0	70	0	0
T156	0	18	0	0
T172	0	42	0	0
T173	0	50	0	0
T174	0	40	0	0
T175	0	19	0	0
T176	0	42	0	0
T177	0	30	0	0
T178	6516	0	0	0
T179	12454	0	0	0
T180	5117	0	0	0
T181	7566	0	0	0
T182	7481	0	0	0
T183	10221	0	0	0
T184	5338	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21268967	3236	0	0
T120	50944	50	0	0
T121	30289	0	0	0
T122	22442	0	0	0
T123	0	2	0	0
T151	0	82	0	0
T156	0	9	0	0
T172	0	40	0	0
T173	0	30	0	0
T174	0	41	0	0
T175	0	23	0	0
T176	0	79	0	0
T177	0	89	0	0
T178	6516	0	0	0
T179	12454	0	0	0
T180	5117	0	0	0
T181	7566	0	0	0
T182	7481	0	0	0
T183	10221	0	0	0
T184	5338	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21268967	3190	0	0
T120	50944	74	0	0
T121	30289	0	0	0
T122	22442	0	0	0
T123	0	6	0	0
T151	0	86	0	0
T156	0	3	0	0
T172	0	66	0	0
T173	0	32	0	0
T174	0	59	0	0
T175	0	26	0	0
T176	0	33	0	0
T177	0	59	0	0
T178	6516	0	0	0
T179	12454	0	0	0
T180	5117	0	0	0
T181	7566	0	0	0
T182	7481	0	0	0
T183	10221	0	0	0
T184	5338	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21268967	3125	0	0
T120	50944	49	0	0
T121	30289	0	0	0
T122	22442	0	0	0
T123	0	25	0	0
T151	0	57	0	0
T156	0	4	0	0
T172	0	41	0	0
T173	0	26	0	0
T174	0	46	0	0
T175	0	38	0	0
T176	0	57	0	0
T177	0	57	0	0
T178	6516	0	0	0
T179	12454	0	0	0
T180	5117	0	0	0
T181	7566	0	0	0
T182	7481	0	0	0
T183	10221	0	0	0
T184	5338	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21268967	3207	0	0
T120	50944	50	0	0
T121	30289	0	0	0
T122	22442	0	0	0
T123	0	26	0	0
T151	0	82	0	0
T156	0	12	0	0
T172	0	56	0	0
T173	0	45	0	0
T174	0	36	0	0
T175	0	15	0	0
T176	0	45	0	0
T177	0	55	0	0
T178	6516	0	0	0
T179	12454	0	0	0
T180	5117	0	0	0
T181	7566	0	0	0
T182	7481	0	0	0
T183	10221	0	0	0
T184	5338	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21268967	3145	0	0
T120	50944	80	0	0
T121	30289	0	0	0
T122	22442	0	0	0
T123	0	25	0	0
T151	0	79	0	0
T156	0	1	0	0
T172	0	64	0	0
T173	0	22	0	0
T174	0	59	0	0
T175	0	44	0	0
T176	0	44	0	0
T177	0	52	0	0
T178	6516	0	0	0
T179	12454	0	0	0
T180	5117	0	0	0
T181	7566	0	0	0
T182	7481	0	0	0
T183	10221	0	0	0
T184	5338	0	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21268967	3025	0	0
T120	50944	55	0	0
T121	30289	0	0	0
T122	22442	0	0	0
T123	0	10	0	0
T151	0	97	0	0
T156	0	6	0	0
T172	0	66	0	0
T173	0	26	0	0
T174	0	71	0	0
T175	0	22	0	0
T176	0	67	0	0
T177	0	44	0	0
T178	6516	0	0	0
T179	12454	0	0	0
T180	5117	0	0	0
T181	7566	0	0	0
T182	7481	0	0	0
T183	10221	0	0	0
T184	5338	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21268967	3112	0	0
T120	50944	49	0	0
T121	30289	0	0	0
T122	22442	0	0	0
T123	0	10	0	0
T151	0	80	0	0
T156	0	6	0	0
T172	0	31	0	0
T173	0	11	0	0
T174	0	70	0	0
T175	0	22	0	0
T176	0	55	0	0
T177	0	59	0	0
T178	6516	0	0	0
T179	12454	0	0	0
T180	5117	0	0	0
T181	7566	0	0	0
T182	7481	0	0	0
T183	10221	0	0	0
T184	5338	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21268967	3217	0	0
T120	50944	68	0	0
T121	30289	0	0	0
T122	22442	0	0	0
T123	0	21	0	0
T151	0	88	0	0
T156	0	7	0	0
T172	0	75	0	0
T173	0	31	0	0
T174	0	60	0	0
T175	0	42	0	0
T176	0	65	0	0
T177	0	55	0	0
T178	6516	0	0	0
T179	12454	0	0	0
T180	5117	0	0	0
T181	7566	0	0	0
T182	7481	0	0	0
T183	10221	0	0	0
T184	5338	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21268967	3365	0	0
T120	50944	59	0	0
T121	30289	0	0	0
T122	22442	0	0	0
T123	0	13	0	0
T151	0	75	0	0
T156	0	6	0	0
T172	0	54	0	0
T173	0	36	0	0
T174	0	47	0	0
T175	0	15	0	0
T176	0	58	0	0
T177	0	69	0	0
T178	6516	0	0	0
T179	12454	0	0	0
T180	5117	0	0	0
T181	7566	0	0	0
T182	7481	0	0	0
T183	10221	0	0	0
T184	5338	0	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21268967	3281	0	0
T120	50944	78	0	0
T121	30289	0	0	0
T122	22442	0	0	0
T123	0	34	0	0
T151	0	72	0	0
T156	0	4	0	0
T172	0	44	0	0
T173	0	29	0	0
T174	0	49	0	0
T175	0	42	0	0
T176	0	75	0	0
T177	0	56	0	0
T178	6516	0	0	0
T179	12454	0	0	0
T180	5117	0	0	0
T181	7566	0	0	0
T182	7481	0	0	0
T183	10221	0	0	0
T184	5338	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21268967	3143	0	0
T120	50944	65	0	0
T121	30289	0	0	0
T122	22442	0	0	0
T123	0	22	0	0
T151	0	89	0	0
T156	0	4	0	0
T172	0	40	0	0
T173	0	23	0	0
T174	0	86	0	0
T175	0	24	0	0
T176	0	33	0	0
T177	0	79	0	0
T178	6516	0	0	0
T179	12454	0	0	0
T180	5117	0	0	0
T181	7566	0	0	0
T182	7481	0	0	0
T183	10221	0	0	0
T184	5338	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21268967	3300	0	0
T120	50944	56	0	0
T121	30289	0	0	0
T122	22442	0	0	0
T123	0	32	0	0
T151	0	81	0	0
T156	0	10	0	0
T172	0	41	0	0
T173	0	28	0	0
T174	0	67	0	0
T175	0	48	0	0
T176	0	47	0	0
T177	0	60	0	0
T178	6516	0	0	0
T179	12454	0	0	0
T180	5117	0	0	0
T181	7566	0	0	0
T182	7481	0	0	0
T183	10221	0	0	0
T184	5338	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21268967	3099	0	0
T120	50944	59	0	0
T121	30289	0	0	0
T122	22442	0	0	0
T123	0	23	0	0
T151	0	64	0	0
T156	0	15	0	0
T172	0	68	0	0
T173	0	30	0	0
T174	0	54	0	0
T175	0	43	0	0
T176	0	59	0	0
T177	0	80	0	0
T178	6516	0	0	0
T179	12454	0	0	0
T180	5117	0	0	0
T181	7566	0	0	0
T182	7481	0	0	0
T183	10221	0	0	0
T184	5338	0	0	0