Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3764050	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

652951

1

T1

283

T2

2096

T3

219

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3973616	1			T1	410		T2	2741		T3	232
values[0x0]	220049	1			T1	117		T2	679		T3	94
values[0x1]	223336	1			T1	110		T2	701		T3	106

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2571155	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1845846

1

T1

370

T2

2644

T3

263

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14726	1			T2	11		T3	2		T13	59
valid_sources[0x01]	15506	1			T2	3		T13	12		T14	4
valid_sources[0x02]	15064	1			T1	1		T2	18		T3	14
valid_sources[0x03]	16251	1			T1	3		T2	23		T13	31
valid_sources[0x04]	18976	1			T2	25		T3	1		T13	14
valid_sources[0x05]	16705	1			T1	4		T2	11		T13	1
valid_sources[0x06]	14036	1			T2	20		T13	5		T17	3
valid_sources[0x07]	25716	1			T2	4		T3	1		T14	1
valid_sources[0x08]	16252	1			T1	15		T2	27		T13	2
valid_sources[0x09]	16728	1			T2	22		T3	2		T13	40
valid_sources[0x0a]	14966	1			T2	14		T13	23		T17	3
valid_sources[0x0b]	15733	1			T1	1		T2	26		T13	8
valid_sources[0x0c]	16057	1			T1	5		T2	26		T3	5
valid_sources[0x0d]	16734	1			T1	2		T2	25		T13	6
valid_sources[0x0e]	15867	1			T1	8		T2	9		T13	18
valid_sources[0x0f]	14449	1			T2	8		T3	2		T15	3
valid_sources[0x10]	15349	1			T1	4		T2	21		T3	3
valid_sources[0x11]	16119	1			T2	7		T13	19		T15	3
valid_sources[0x12]	14369	1			T2	36		T3	3		T13	5
valid_sources[0x13]	15048	1			T2	4		T13	8		T15	1
valid_sources[0x14]	17393	1			T2	20		T13	1		T15	4
valid_sources[0x15]	15826	1			T1	11		T2	12		T13	8
valid_sources[0x16]	17258	1			T2	23		T13	6		T14	3
valid_sources[0x17]	16892	1			T2	32		T3	1		T13	17
valid_sources[0x18]	14644	1			T1	3		T2	4		T3	5
valid_sources[0x19]	14625	1			T1	2		T2	13		T13	11
valid_sources[0x1a]	30937	1			T2	2		T3	11		T13	59
valid_sources[0x1b]	13930	1			T1	2		T2	8		T13	25
valid_sources[0x1c]	13688	1			T2	5		T3	12		T15	5
valid_sources[0x1d]	14174	1			T1	3		T2	6		T13	29
valid_sources[0x1e]	14563	1			T2	14		T13	13		T14	1
valid_sources[0x1f]	14976	1			T1	2		T2	20		T3	2
valid_sources[0x20]	16237	1			T1	4		T2	18		T3	8
valid_sources[0x21]	18907	1			T2	7		T13	11		T18	4
valid_sources[0x22]	14888	1			T1	1		T2	13		T13	6
valid_sources[0x23]	16714	1			T1	1		T2	3		T13	36
valid_sources[0x24]	15795	1			T1	10		T2	12		T3	1
valid_sources[0x25]	14534	1			T1	4		T2	19		T3	3
valid_sources[0x26]	22708	1			T2	16		T15	3		T19	8
valid_sources[0x27]	14125	1			T2	5		T13	32		T14	7
valid_sources[0x28]	14998	1			T2	22		T13	6		T15	4
valid_sources[0x29]	14771	1			T1	5		T2	27		T13	25
valid_sources[0x2a]	35924	1			T1	1		T2	6		T16	1
valid_sources[0x2b]	15916	1			T1	6		T2	8		T13	3
valid_sources[0x2c]	14886	1			T1	16		T2	13		T3	7
valid_sources[0x2d]	23383	1			T1	2		T2	15		T13	15
valid_sources[0x2e]	14672	1			T1	5		T2	17		T3	7
valid_sources[0x2f]	16723	1			T1	1		T2	9		T13	12
valid_sources[0x30]	14913	1			T1	8		T2	5		T13	5
valid_sources[0x31]	14616	1			T2	30		T3	2		T13	9
valid_sources[0x32]	15237	1			T1	1		T2	20		T13	10
valid_sources[0x33]	15491	1			T1	6		T2	6		T3	1
valid_sources[0x34]	13966	1			T1	2		T2	36		T13	13
valid_sources[0x35]	14609	1			T1	5		T2	8		T13	9
valid_sources[0x36]	14686	1			T2	7		T13	4		T15	5
valid_sources[0x37]	17235	1			T2	17		T13	14		T15	3
valid_sources[0x38]	14611	1			T1	5		T2	15		T13	40
valid_sources[0x39]	15261	1			T2	16		T13	13		T15	4
valid_sources[0x3a]	17552	1			T1	1		T2	18		T13	23
valid_sources[0x3b]	31218	1			T1	2		T2	4		T13	2
valid_sources[0x3c]	14745	1			T1	6		T2	28		T13	15
valid_sources[0x3d]	19735	1			T2	9		T3	6		T13	2
valid_sources[0x3e]	18556	1			T1	6		T2	10		T3	1
valid_sources[0x3f]	17382	1			T2	10		T3	5		T13	9
valid_sources[0x40]	14638	1			T2	10		T3	2		T13	5
valid_sources[0x41]	14115	1			T2	23		T15	3		T16	1
valid_sources[0x42]	14922	1			T2	17		T3	2		T13	102
valid_sources[0x43]	17115	1			T1	7		T2	13		T3	3
valid_sources[0x44]	15901	1			T1	4		T2	37		T13	2
valid_sources[0x45]	15231	1			T1	2		T2	2		T13	30
valid_sources[0x46]	14395	1			T2	80		T3	8		T14	2
valid_sources[0x47]	17604	1			T2	18		T15	1		T16	4
valid_sources[0x48]	19260	1			T3	4		T13	33		T14	21
valid_sources[0x49]	14581	1			T2	9		T3	1		T14	2
valid_sources[0x4a]	14365	1			T1	4		T2	16		T13	12
valid_sources[0x4b]	15774	1			T1	6		T2	18		T3	6
valid_sources[0x4c]	18262	1			T1	2		T2	27		T15	2
valid_sources[0x4d]	22257	1			T1	6		T2	16		T3	5
valid_sources[0x4e]	14337	1			T2	23		T3	2		T13	8
valid_sources[0x4f]	18652	1			T2	28		T13	43		T14	2
valid_sources[0x50]	18300	1			T1	1		T2	15		T3	8
valid_sources[0x51]	14070	1			T1	1		T2	42		T13	2
valid_sources[0x52]	14602	1			T2	9		T3	1		T15	2
valid_sources[0x53]	14247	1			T1	9		T2	6		T13	40
valid_sources[0x54]	17102	1			T1	5		T2	4		T3	1
valid_sources[0x55]	16718	1			T2	4		T13	10		T15	2
valid_sources[0x56]	14093	1			T1	2		T2	20		T13	40
valid_sources[0x57]	15805	1			T1	2		T2	17		T13	32
valid_sources[0x58]	14965	1			T1	10		T2	31		T13	16
valid_sources[0x59]	17855	1			T1	6		T2	5		T3	1
valid_sources[0x5a]	15465	1			T2	18		T3	6		T13	13
valid_sources[0x5b]	79765	1			T1	6		T2	25		T13	9
valid_sources[0x5c]	15335	1			T1	9		T2	14		T13	9
valid_sources[0x5d]	20235	1			T1	5		T2	9		T13	6
valid_sources[0x5e]	19965	1			T2	35		T14	5		T15	1
valid_sources[0x5f]	27149	1			T1	1		T2	21		T13	10
valid_sources[0x60]	15272	1			T2	49		T13	24		T15	3
valid_sources[0x61]	15620	1			T2	12		T3	1		T13	12
valid_sources[0x62]	14163	1			T2	48		T3	1		T14	3
valid_sources[0x63]	19815	1			T2	32		T3	2		T13	4
valid_sources[0x64]	27684	1			T1	2		T2	20		T3	1
valid_sources[0x65]	14159	1			T2	5		T3	2		T13	12
valid_sources[0x66]	14477	1			T2	18		T3	2		T13	3
valid_sources[0x67]	15487	1			T2	55		T13	4		T14	2
valid_sources[0x68]	14685	1			T1	5		T2	39		T13	12
valid_sources[0x69]	15081	1			T13	13		T14	14		T15	4
valid_sources[0x6a]	16318	1			T2	32		T3	4		T13	11
valid_sources[0x6b]	14394	1			T1	9		T2	11		T13	18
valid_sources[0x6c]	25955	1			T1	6		T2	8		T3	6
valid_sources[0x6d]	15443	1			T1	6		T2	11		T3	3
valid_sources[0x6e]	13973	1			T2	27		T13	23		T17	2
valid_sources[0x6f]	15678	1			T2	13		T3	3		T13	52
valid_sources[0x70]	14864	1			T2	28		T3	1		T13	3
valid_sources[0x71]	15623	1			T1	1		T2	19		T3	1
valid_sources[0x72]	16447	1			T1	7		T2	30		T13	6
valid_sources[0x73]	14676	1			T1	2		T13	21		T17	4
valid_sources[0x74]	16267	1			T1	7		T2	2		T3	1
valid_sources[0x75]	14251	1			T2	41		T13	13		T14	2
valid_sources[0x76]	16420	1			T1	11		T2	37		T3	2
valid_sources[0x77]	20410	1			T2	3		T3	2		T13	15
valid_sources[0x78]	14275	1			T1	10		T2	15		T13	5
valid_sources[0x79]	14597	1			T2	34		T3	4		T13	21
valid_sources[0x7a]	16238	1			T2	17		T3	1		T13	12
valid_sources[0x7b]	15121	1			T1	4		T2	15		T13	2
valid_sources[0x7c]	19239	1			T1	9		T2	35		T13	32
valid_sources[0x7d]	17672	1			T2	13		T3	5		T13	52
valid_sources[0x7e]	25749	1			T1	8		T2	4		T13	14
valid_sources[0x7f]	16749	1			T1	1		T2	3		T3	2
valid_sources[0x80]	17919	1			T1	3		T2	9		T15	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

352341

1

T1

142

T2

1128

T3

88

values[0x0]

all_enables

biggest_size

158190

1

T1

78

T2

526

T3

60

values[0x1]

all_enables

biggest_size

142420

1

T1

63

T2

442

T3

71