Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	27551202	18773	0	0
attest_sw_binding_0_rd_A	27551202	3606	0	0
attest_sw_binding_1_rd_A	27551202	3613	0	0
attest_sw_binding_2_rd_A	27551202	3779	0	0
attest_sw_binding_3_rd_A	27551202	3690	0	0
attest_sw_binding_4_rd_A	27551202	3704	0	0
attest_sw_binding_5_rd_A	27551202	3564	0	0
attest_sw_binding_6_rd_A	27551202	3424	0	0
attest_sw_binding_7_rd_A	27551202	3511	0	0
intr_enable_rd_A	27551202	4236	0	0
key_version_rd_A	27551202	3618	0	0
max_creator_key_ver_regwen_rd_A	27551202	3611	0	0
max_owner_int_key_ver_regwen_rd_A	27551202	3376	0	0
max_owner_key_ver_regwen_rd_A	27551202	3697	0	0
reseed_interval_regwen_rd_A	27551202	3455	0	0
salt_0_rd_A	27551202	3633	0	0
salt_1_rd_A	27551202	3533	0	0
salt_2_rd_A	27551202	3545	0	0
salt_3_rd_A	27551202	3470	0	0
salt_4_rd_A	27551202	3396	0	0
salt_5_rd_A	27551202	3748	0	0
salt_6_rd_A	27551202	3640	0	0
salt_7_rd_A	27551202	3543	0	0
sealing_sw_binding_0_rd_A	27551202	3613	0	0
sealing_sw_binding_1_rd_A	27551202	3572	0	0
sealing_sw_binding_2_rd_A	27551202	3619	0	0
sealing_sw_binding_3_rd_A	27551202	3653	0	0
sealing_sw_binding_4_rd_A	27551202	3562	0	0
sealing_sw_binding_5_rd_A	27551202	3505	0	0
sealing_sw_binding_6_rd_A	27551202	3638	0	0
sealing_sw_binding_7_rd_A	27551202	3573	0	0
sideload_clear_rd_A	27551202	3679	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27551202	18773	0	0
T2	37485	351	0	0
T3	2646	0	0	0
T13	21514	789	0	0
T14	2862	0	0	0
T15	5390	0	0	0
T16	19413	0	0	0
T17	6875	0	0	0
T18	19493	0	0	0
T19	8559	0	0	0
T52	0	592	0	0
T68	0	52	0	0
T69	0	654	0	0
T74	0	608	0	0
T75	0	91	0	0
T87	113838	0	0	0
T105	0	1	0	0
T118	0	74	0	0
T119	0	439	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27551202	3606	0	0
T30	4219	0	0	0
T68	57039	24	0	0
T119	0	65	0	0
T130	166714	0	0	0
T170	0	34	0	0
T171	0	38	0	0
T172	0	55	0	0
T173	0	18	0	0
T174	0	80	0	0
T175	0	54	0	0
T176	0	35	0	0
T177	0	26	0	0
T178	8662	0	0	0
T179	5080	0	0	0
T180	8399	0	0	0
T181	1246	0	0	0
T182	626	0	0	0
T183	11549	0	0	0
T184	1017	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27551202	3613	0	0
T30	4219	0	0	0
T68	57039	23	0	0
T119	0	48	0	0
T130	166714	0	0	0
T170	0	12	0	0
T171	0	33	0	0
T172	0	63	0	0
T173	0	18	0	0
T174	0	41	0	0
T175	0	63	0	0
T176	0	36	0	0
T177	0	30	0	0
T178	8662	0	0	0
T179	5080	0	0	0
T180	8399	0	0	0
T181	1246	0	0	0
T182	626	0	0	0
T183	11549	0	0	0
T184	1017	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27551202	3779	0	0
T25	16013	0	0	0
T43	2637	0	0	0
T46	132640	0	0	0
T52	24340	0	0	0
T54	5482	1	0	0
T68	0	17	0	0
T80	19279	0	0	0
T81	8077	0	0	0
T101	2511	0	0	0
T119	0	95	0	0
T140	134168	0	0	0
T170	0	22	0	0
T171	0	13	0	0
T172	0	51	0	0
T173	0	23	0	0
T174	0	61	0	0
T175	0	62	0	0
T176	0	32	0	0
T185	10909	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27551202	3690	0	0
T30	4219	0	0	0
T68	57039	26	0	0
T119	0	65	0	0
T130	166714	0	0	0
T170	0	11	0	0
T171	0	12	0	0
T172	0	68	0	0
T173	0	33	0	0
T174	0	54	0	0
T175	0	60	0	0
T176	0	24	0	0
T177	0	38	0	0
T178	8662	0	0	0
T179	5080	0	0	0
T180	8399	0	0	0
T181	1246	0	0	0
T182	626	0	0	0
T183	11549	0	0	0
T184	1017	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27551202	3704	0	0
T30	4219	0	0	0
T68	57039	12	0	0
T119	0	74	0	0
T130	166714	0	0	0
T170	0	25	0	0
T171	0	59	0	0
T172	0	58	0	0
T173	0	40	0	0
T174	0	60	0	0
T175	0	56	0	0
T176	0	42	0	0
T177	0	26	0	0
T178	8662	0	0	0
T179	5080	0	0	0
T180	8399	0	0	0
T181	1246	0	0	0
T182	626	0	0	0
T183	11549	0	0	0
T184	1017	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27551202	3564	0	0
T30	4219	0	0	0
T68	57039	30	0	0
T119	0	68	0	0
T130	166714	0	0	0
T170	0	40	0	0
T171	0	25	0	0
T172	0	46	0	0
T173	0	9	0	0
T174	0	79	0	0
T175	0	59	0	0
T176	0	37	0	0
T177	0	41	0	0
T178	8662	0	0	0
T179	5080	0	0	0
T180	8399	0	0	0
T181	1246	0	0	0
T182	626	0	0	0
T183	11549	0	0	0
T184	1017	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27551202	3424	0	0
T30	4219	0	0	0
T68	57039	28	0	0
T119	0	60	0	0
T130	166714	0	0	0
T170	0	15	0	0
T171	0	36	0	0
T172	0	56	0	0
T173	0	16	0	0
T174	0	47	0	0
T175	0	57	0	0
T176	0	15	0	0
T177	0	27	0	0
T178	8662	0	0	0
T179	5080	0	0	0
T180	8399	0	0	0
T181	1246	0	0	0
T182	626	0	0	0
T183	11549	0	0	0
T184	1017	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27551202	3511	0	0
T30	4219	0	0	0
T68	57039	25	0	0
T119	0	65	0	0
T130	166714	0	0	0
T170	0	3	0	0
T171	0	38	0	0
T172	0	42	0	0
T173	0	12	0	0
T174	0	52	0	0
T175	0	45	0	0
T176	0	48	0	0
T177	0	23	0	0
T178	8662	0	0	0
T179	5080	0	0	0
T180	8399	0	0	0
T181	1246	0	0	0
T182	626	0	0	0
T183	11549	0	0	0
T184	1017	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27551202	4236	0	0
T23	12719	0	0	0
T24	24807	0	0	0
T36	2617	0	0	0
T37	8572	0	0	0
T44	391563	22	0	0
T45	0	63	0	0
T65	0	11	0	0
T68	0	16	0	0
T71	0	2	0	0
T119	0	85	0	0
T122	6407	0	0	0
T123	5191	0	0	0
T124	12826	0	0	0
T125	20060	0	0	0
T126	18764	0	0	0
T186	0	28	0	0
T187	0	23	0	0
T188	0	25	0	0
T189	0	52	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27551202	3618	0	0
T30	4219	0	0	0
T68	57039	24	0	0
T119	0	44	0	0
T130	166714	0	0	0
T170	0	11	0	0
T171	0	34	0	0
T172	0	57	0	0
T173	0	24	0	0
T174	0	81	0	0
T175	0	55	0	0
T176	0	34	0	0
T177	0	29	0	0
T178	8662	0	0	0
T179	5080	0	0	0
T180	8399	0	0	0
T181	1246	0	0	0
T182	626	0	0	0
T183	11549	0	0	0
T184	1017	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27551202	3611	0	0
T30	4219	0	0	0
T68	57039	47	0	0
T119	0	70	0	0
T130	166714	0	0	0
T170	0	22	0	0
T171	0	31	0	0
T172	0	53	0	0
T173	0	6	0	0
T174	0	44	0	0
T175	0	85	0	0
T176	0	24	0	0
T177	0	11	0	0
T178	8662	0	0	0
T179	5080	0	0	0
T180	8399	0	0	0
T181	1246	0	0	0
T182	626	0	0	0
T183	11549	0	0	0
T184	1017	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27551202	3376	0	0
T30	4219	0	0	0
T68	57039	29	0	0
T119	0	60	0	0
T130	166714	0	0	0
T170	0	15	0	0
T171	0	29	0	0
T172	0	65	0	0
T173	0	28	0	0
T174	0	37	0	0
T175	0	36	0	0
T176	0	30	0	0
T177	0	19	0	0
T178	8662	0	0	0
T179	5080	0	0	0
T180	8399	0	0	0
T181	1246	0	0	0
T182	626	0	0	0
T183	11549	0	0	0
T184	1017	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27551202	3697	0	0
T30	4219	0	0	0
T68	57039	25	0	0
T119	0	80	0	0
T130	166714	0	0	0
T170	0	21	0	0
T171	0	57	0	0
T172	0	78	0	0
T173	0	15	0	0
T174	0	62	0	0
T175	0	48	0	0
T176	0	20	0	0
T177	0	31	0	0
T178	8662	0	0	0
T179	5080	0	0	0
T180	8399	0	0	0
T181	1246	0	0	0
T182	626	0	0	0
T183	11549	0	0	0
T184	1017	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27551202	3455	0	0
T30	4219	0	0	0
T68	57039	36	0	0
T119	0	54	0	0
T130	166714	0	0	0
T170	0	13	0	0
T171	0	30	0	0
T172	0	74	0	0
T173	0	22	0	0
T174	0	51	0	0
T175	0	54	0	0
T176	0	19	0	0
T178	8662	0	0	0
T179	5080	0	0	0
T180	8399	0	0	0
T181	1246	0	0	0
T182	626	0	0	0
T183	11549	0	0	0
T184	1017	0	0	0
T190	0	1	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27551202	3633	0	0
T30	4219	0	0	0
T68	57039	21	0	0
T119	0	48	0	0
T130	166714	0	0	0
T170	0	18	0	0
T171	0	19	0	0
T172	0	50	0	0
T173	0	27	0	0
T174	0	65	0	0
T175	0	62	0	0
T176	0	24	0	0
T177	0	31	0	0
T178	8662	0	0	0
T179	5080	0	0	0
T180	8399	0	0	0
T181	1246	0	0	0
T182	626	0	0	0
T183	11549	0	0	0
T184	1017	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27551202	3533	0	0
T30	4219	0	0	0
T68	57039	21	0	0
T119	0	80	0	0
T130	166714	0	0	0
T170	0	8	0	0
T171	0	35	0	0
T172	0	66	0	0
T173	0	35	0	0
T174	0	44	0	0
T175	0	40	0	0
T176	0	58	0	0
T177	0	19	0	0
T178	8662	0	0	0
T179	5080	0	0	0
T180	8399	0	0	0
T181	1246	0	0	0
T182	626	0	0	0
T183	11549	0	0	0
T184	1017	0	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27551202	3545	0	0
T30	4219	0	0	0
T68	57039	17	0	0
T119	0	61	0	0
T130	166714	0	0	0
T170	0	4	0	0
T171	0	15	0	0
T172	0	57	0	0
T173	0	31	0	0
T174	0	52	0	0
T175	0	41	0	0
T176	0	25	0	0
T177	0	22	0	0
T178	8662	0	0	0
T179	5080	0	0	0
T180	8399	0	0	0
T181	1246	0	0	0
T182	626	0	0	0
T183	11549	0	0	0
T184	1017	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27551202	3470	0	0
T30	4219	0	0	0
T68	57039	34	0	0
T119	0	63	0	0
T130	166714	0	0	0
T170	0	18	0	0
T171	0	26	0	0
T172	0	53	0	0
T173	0	15	0	0
T174	0	49	0	0
T175	0	57	0	0
T176	0	46	0	0
T177	0	50	0	0
T178	8662	0	0	0
T179	5080	0	0	0
T180	8399	0	0	0
T181	1246	0	0	0
T182	626	0	0	0
T183	11549	0	0	0
T184	1017	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27551202	3396	0	0
T30	4219	0	0	0
T68	57039	31	0	0
T119	0	95	0	0
T130	166714	0	0	0
T170	0	12	0	0
T171	0	25	0	0
T172	0	45	0	0
T173	0	13	0	0
T174	0	54	0	0
T175	0	58	0	0
T176	0	30	0	0
T177	0	25	0	0
T178	8662	0	0	0
T179	5080	0	0	0
T180	8399	0	0	0
T181	1246	0	0	0
T182	626	0	0	0
T183	11549	0	0	0
T184	1017	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27551202	3748	0	0
T30	4219	0	0	0
T68	57039	44	0	0
T119	0	86	0	0
T130	166714	0	0	0
T170	0	14	0	0
T171	0	33	0	0
T172	0	51	0	0
T173	0	28	0	0
T174	0	75	0	0
T175	0	42	0	0
T176	0	30	0	0
T178	8662	0	0	0
T179	5080	0	0	0
T180	8399	0	0	0
T181	1246	0	0	0
T182	626	0	0	0
T183	11549	0	0	0
T184	1017	0	0	0
T191	0	7	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27551202	3640	0	0
T30	4219	0	0	0
T68	57039	54	0	0
T119	0	67	0	0
T130	166714	0	0	0
T170	0	7	0	0
T171	0	19	0	0
T172	0	60	0	0
T173	0	22	0	0
T174	0	55	0	0
T175	0	46	0	0
T176	0	33	0	0
T177	0	17	0	0
T178	8662	0	0	0
T179	5080	0	0	0
T180	8399	0	0	0
T181	1246	0	0	0
T182	626	0	0	0
T183	11549	0	0	0
T184	1017	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27551202	3543	0	0
T30	4219	0	0	0
T68	57039	50	0	0
T119	0	70	0	0
T130	166714	0	0	0
T170	0	6	0	0
T171	0	30	0	0
T172	0	32	0	0
T173	0	33	0	0
T174	0	52	0	0
T175	0	29	0	0
T176	0	18	0	0
T177	0	25	0	0
T178	8662	0	0	0
T179	5080	0	0	0
T180	8399	0	0	0
T181	1246	0	0	0
T182	626	0	0	0
T183	11549	0	0	0
T184	1017	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27551202	3613	0	0
T30	4219	0	0	0
T68	57039	32	0	0
T119	0	60	0	0
T130	166714	0	0	0
T170	0	16	0	0
T171	0	23	0	0
T172	0	32	0	0
T173	0	14	0	0
T174	0	58	0	0
T175	0	49	0	0
T176	0	41	0	0
T177	0	25	0	0
T178	8662	0	0	0
T179	5080	0	0	0
T180	8399	0	0	0
T181	1246	0	0	0
T182	626	0	0	0
T183	11549	0	0	0
T184	1017	0	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27551202	3572	0	0
T30	4219	0	0	0
T68	57039	37	0	0
T119	0	59	0	0
T130	166714	0	0	0
T170	0	12	0	0
T171	0	19	0	0
T172	0	38	0	0
T173	0	16	0	0
T174	0	58	0	0
T175	0	50	0	0
T176	0	54	0	0
T177	0	29	0	0
T178	8662	0	0	0
T179	5080	0	0	0
T180	8399	0	0	0
T181	1246	0	0	0
T182	626	0	0	0
T183	11549	0	0	0
T184	1017	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27551202	3619	0	0
T30	4219	0	0	0
T68	57039	51	0	0
T119	0	64	0	0
T130	166714	0	0	0
T170	0	21	0	0
T171	0	29	0	0
T172	0	68	0	0
T173	0	15	0	0
T174	0	55	0	0
T175	0	73	0	0
T176	0	34	0	0
T177	0	12	0	0
T178	8662	0	0	0
T179	5080	0	0	0
T180	8399	0	0	0
T181	1246	0	0	0
T182	626	0	0	0
T183	11549	0	0	0
T184	1017	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27551202	3653	0	0
T30	4219	0	0	0
T68	57039	14	0	0
T119	0	60	0	0
T130	166714	0	0	0
T170	0	24	0	0
T171	0	42	0	0
T172	0	56	0	0
T173	0	39	0	0
T174	0	74	0	0
T175	0	58	0	0
T176	0	24	0	0
T177	0	17	0	0
T178	8662	0	0	0
T179	5080	0	0	0
T180	8399	0	0	0
T181	1246	0	0	0
T182	626	0	0	0
T183	11549	0	0	0
T184	1017	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27551202	3562	0	0
T30	4219	0	0	0
T68	57039	30	0	0
T119	0	53	0	0
T130	166714	0	0	0
T170	0	13	0	0
T171	0	53	0	0
T172	0	40	0	0
T173	0	27	0	0
T174	0	44	0	0
T175	0	78	0	0
T176	0	21	0	0
T177	0	20	0	0
T178	8662	0	0	0
T179	5080	0	0	0
T180	8399	0	0	0
T181	1246	0	0	0
T182	626	0	0	0
T183	11549	0	0	0
T184	1017	0	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27551202	3505	0	0
T30	4219	0	0	0
T68	57039	18	0	0
T119	0	45	0	0
T130	166714	0	0	0
T170	0	15	0	0
T171	0	43	0	0
T172	0	60	0	0
T173	0	20	0	0
T174	0	84	0	0
T175	0	54	0	0
T176	0	35	0	0
T177	0	7	0	0
T178	8662	0	0	0
T179	5080	0	0	0
T180	8399	0	0	0
T181	1246	0	0	0
T182	626	0	0	0
T183	11549	0	0	0
T184	1017	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27551202	3638	0	0
T30	4219	0	0	0
T68	57039	34	0	0
T119	0	65	0	0
T130	166714	0	0	0
T170	0	35	0	0
T171	0	61	0	0
T172	0	81	0	0
T173	0	12	0	0
T174	0	48	0	0
T175	0	58	0	0
T176	0	26	0	0
T177	0	10	0	0
T178	8662	0	0	0
T179	5080	0	0	0
T180	8399	0	0	0
T181	1246	0	0	0
T182	626	0	0	0
T183	11549	0	0	0
T184	1017	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27551202	3573	0	0
T30	4219	0	0	0
T68	57039	30	0	0
T119	0	74	0	0
T130	166714	0	0	0
T170	0	14	0	0
T171	0	37	0	0
T172	0	63	0	0
T173	0	21	0	0
T174	0	44	0	0
T175	0	47	0	0
T176	0	28	0	0
T177	0	23	0	0
T178	8662	0	0	0
T179	5080	0	0	0
T180	8399	0	0	0
T181	1246	0	0	0
T182	626	0	0	0
T183	11549	0	0	0
T184	1017	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27551202	3679	0	0
T30	4219	0	0	0
T68	57039	30	0	0
T119	0	76	0	0
T130	166714	0	0	0
T170	0	15	0	0
T171	0	25	0	0
T172	0	60	0	0
T173	0	29	0	0
T174	0	60	0	0
T175	0	40	0	0
T176	0	19	0	0
T177	0	26	0	0
T178	8662	0	0	0
T179	5080	0	0	0
T180	8399	0	0	0
T181	1246	0	0	0
T182	626	0	0	0
T183	11549	0	0	0
T184	1017	0	0	0