Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2788553	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

633875

1

T1

719

T2

464

T3

364

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2998524	1			T1	1574		T2	676		T3	1324
values[0x0]	209924	1			T1	294		T2	149		T3	175
values[0x1]	213980	1			T1	292		T2	141		T3	170

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1921565	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1500863

1

T1

1133

T2

598

T3

777

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12525	1			T1	7		T2	2		T3	3
valid_sources[0x01]	11142	1			T2	8		T3	8		T13	1
valid_sources[0x02]	16419	1			T1	13		T2	2		T14	4
valid_sources[0x03]	12912	1			T1	7		T2	1		T4	45
valid_sources[0x04]	11826	1			T1	1		T2	10		T3	8
valid_sources[0x05]	10694	1			T1	3		T2	8		T3	3
valid_sources[0x06]	14177	1			T2	4		T13	2		T4	52
valid_sources[0x07]	24671	1			T1	2		T2	16		T3	3
valid_sources[0x08]	10434	1			T1	4		T2	1		T3	19
valid_sources[0x09]	11780	1			T1	6		T3	15		T4	26
valid_sources[0x0a]	11043	1			T3	12		T13	2		T4	41
valid_sources[0x0b]	11089	1			T3	2		T13	5		T4	36
valid_sources[0x0c]	12329	1			T1	41		T2	1		T3	3
valid_sources[0x0d]	11116	1			T1	11		T3	5		T4	38
valid_sources[0x0e]	10780	1			T1	16		T2	2		T3	4
valid_sources[0x0f]	16938	1			T2	2		T3	5		T13	3
valid_sources[0x10]	11638	1			T1	5		T2	13		T3	8
valid_sources[0x11]	11220	1			T1	22		T2	6		T3	13
valid_sources[0x12]	12770	1			T1	4		T2	2		T3	7
valid_sources[0x13]	15574	1			T2	4		T3	7		T13	4
valid_sources[0x14]	11476	1			T1	8		T2	12		T3	4
valid_sources[0x15]	10729	1			T1	4		T2	5		T3	7
valid_sources[0x16]	10795	1			T2	1		T3	3		T4	33
valid_sources[0x17]	11701	1			T1	10		T3	2		T4	31
valid_sources[0x18]	11754	1			T1	6		T2	8		T3	8
valid_sources[0x19]	11259	1			T1	2		T2	10		T3	10
valid_sources[0x1a]	12906	1			T1	4		T2	4		T3	4
valid_sources[0x1b]	11257	1			T1	10		T2	1		T3	17
valid_sources[0x1c]	10640	1			T1	8		T3	16		T13	1
valid_sources[0x1d]	10755	1			T1	4		T3	8		T4	42
valid_sources[0x1e]	12948	1			T1	18		T2	5		T3	19
valid_sources[0x1f]	11855	1			T2	6		T3	19		T4	34
valid_sources[0x20]	11219	1			T1	17		T2	1		T3	8
valid_sources[0x21]	11073	1			T1	19		T2	6		T3	1
valid_sources[0x22]	11436	1			T1	5		T3	19		T13	1
valid_sources[0x23]	12580	1			T1	1		T3	2		T4	34
valid_sources[0x24]	12713	1			T1	2		T2	5		T3	7
valid_sources[0x25]	12625	1			T1	12		T3	4		T13	1
valid_sources[0x26]	11414	1			T1	17		T3	3		T4	48
valid_sources[0x27]	11523	1			T1	2		T2	3		T13	5
valid_sources[0x28]	18002	1			T1	36		T3	5		T13	2
valid_sources[0x29]	18821	1			T1	13		T2	4		T3	3
valid_sources[0x2a]	12876	1			T1	8		T2	4		T13	1
valid_sources[0x2b]	12262	1			T1	14		T2	2		T3	2
valid_sources[0x2c]	23590	1			T1	7		T2	3		T3	10
valid_sources[0x2d]	12921	1			T1	14		T2	5		T3	7
valid_sources[0x2e]	11465	1			T1	5		T2	10		T3	10
valid_sources[0x2f]	12689	1			T1	4		T2	3		T3	7
valid_sources[0x30]	12712	1			T1	26		T2	4		T3	4
valid_sources[0x31]	11310	1			T2	1		T3	17		T13	9
valid_sources[0x32]	46284	1			T1	3		T3	8		T13	2
valid_sources[0x33]	11914	1			T2	5		T3	6		T13	4
valid_sources[0x34]	11538	1			T1	8		T3	5		T13	2
valid_sources[0x35]	13415	1			T1	4		T2	1		T3	10
valid_sources[0x36]	10683	1			T1	14		T2	5		T3	3
valid_sources[0x37]	11806	1			T1	5		T2	9		T14	4
valid_sources[0x38]	15099	1			T1	13		T2	2		T13	2
valid_sources[0x39]	51413	1			T3	8		T4	48		T16	2
valid_sources[0x3a]	12136	1			T1	23		T2	9		T3	1
valid_sources[0x3b]	11035	1			T1	6		T2	7		T3	6
valid_sources[0x3c]	11727	1			T2	2		T3	6		T13	2
valid_sources[0x3d]	12323	1			T1	3		T2	6		T3	10
valid_sources[0x3e]	12067	1			T1	8		T2	3		T3	12
valid_sources[0x3f]	12164	1			T1	13		T2	2		T3	11
valid_sources[0x40]	10251	1			T1	1		T3	2		T13	1
valid_sources[0x41]	15533	1			T1	8		T2	1		T3	22
valid_sources[0x42]	12943	1			T1	2		T2	8		T3	2
valid_sources[0x43]	12439	1			T1	8		T2	3		T3	12
valid_sources[0x44]	11541	1			T1	14		T2	6		T3	7
valid_sources[0x45]	11202	1			T1	5		T2	8		T3	2
valid_sources[0x46]	10435	1			T2	5		T3	2		T13	2
valid_sources[0x47]	11135	1			T1	7		T2	5		T3	8
valid_sources[0x48]	17882	1			T2	7		T14	13		T4	38
valid_sources[0x49]	15665	1			T1	25		T2	1		T3	8
valid_sources[0x4a]	11907	1			T1	2		T2	3		T3	6
valid_sources[0x4b]	11771	1			T2	1		T3	16		T4	46
valid_sources[0x4c]	12839	1			T1	22		T2	4		T3	11
valid_sources[0x4d]	12320	1			T1	1		T2	6		T3	16
valid_sources[0x4e]	10625	1			T1	13		T2	3		T3	3
valid_sources[0x4f]	11637	1			T1	1		T2	2		T3	7
valid_sources[0x50]	10819	1			T2	3		T3	5		T13	1
valid_sources[0x51]	10676	1			T1	8		T2	1		T3	10
valid_sources[0x52]	15437	1			T1	22		T2	7		T3	3
valid_sources[0x53]	12293	1			T1	1		T2	4		T3	4
valid_sources[0x54]	12318	1			T1	8		T2	1		T3	21
valid_sources[0x55]	25761	1			T1	24		T3	6		T4	30
valid_sources[0x56]	10383	1			T1	12		T3	6		T4	39
valid_sources[0x57]	10809	1			T1	6		T2	8		T3	8
valid_sources[0x58]	12347	1			T1	9		T2	2		T3	2
valid_sources[0x59]	10463	1			T1	17		T2	4		T3	3
valid_sources[0x5a]	10668	1			T1	5		T2	2		T3	11
valid_sources[0x5b]	22558	1			T2	10		T3	5		T13	1
valid_sources[0x5c]	14591	1			T1	10		T3	15		T13	5
valid_sources[0x5d]	11852	1			T1	23		T2	2		T3	1
valid_sources[0x5e]	11537	1			T1	3		T2	1		T3	8
valid_sources[0x5f]	11070	1			T2	8		T3	4		T13	12
valid_sources[0x60]	11940	1			T2	4		T3	5		T13	1
valid_sources[0x61]	11904	1			T1	8		T2	8		T3	2
valid_sources[0x62]	35114	1			T1	8		T2	11		T3	13
valid_sources[0x63]	12040	1			T3	2		T13	1		T14	11
valid_sources[0x64]	11051	1			T1	4		T2	1		T4	41
valid_sources[0x65]	13000	1			T1	5		T2	1		T3	11
valid_sources[0x66]	14819	1			T1	1		T2	3		T3	3
valid_sources[0x67]	12088	1			T1	5		T3	10		T13	1
valid_sources[0x68]	10025	1			T1	13		T2	13		T13	3
valid_sources[0x69]	12119	1			T1	6		T2	5		T3	6
valid_sources[0x6a]	20110	1			T1	9		T2	1		T3	7
valid_sources[0x6b]	10846	1			T1	18		T2	2		T3	18
valid_sources[0x6c]	10301	1			T1	8		T3	3		T4	43
valid_sources[0x6d]	10794	1			T1	7		T2	1		T14	1
valid_sources[0x6e]	13642	1			T1	6		T2	2		T14	3
valid_sources[0x6f]	10652	1			T1	15		T3	4		T13	2
valid_sources[0x70]	16008	1			T1	24		T2	4		T3	17
valid_sources[0x71]	12294	1			T1	1		T2	6		T14	12
valid_sources[0x72]	10831	1			T1	9		T2	6		T3	8
valid_sources[0x73]	12267	1			T1	7		T2	8		T3	2
valid_sources[0x74]	10302	1			T1	7		T2	1		T3	1
valid_sources[0x75]	12040	1			T1	2		T2	10		T3	7
valid_sources[0x76]	11804	1			T1	8		T2	2		T3	8
valid_sources[0x77]	19306	1			T1	22		T2	1		T3	7
valid_sources[0x78]	10614	1			T1	20		T2	4		T3	4
valid_sources[0x79]	10929	1			T1	2		T2	6		T3	11
valid_sources[0x7a]	10717	1			T1	16		T2	6		T3	3
valid_sources[0x7b]	14612	1			T3	13		T13	4		T14	6
valid_sources[0x7c]	11235	1			T2	6		T3	4		T13	4
valid_sources[0x7d]	14860	1			T1	21		T3	13		T4	42
valid_sources[0x7e]	11081	1			T1	2		T2	6		T3	14
valid_sources[0x7f]	11208	1			T1	13		T2	3		T3	12
valid_sources[0x80]	19287	1			T1	9		T3	3		T4	40

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

347414

1

T1

285

T2

252

T3

118

values[0x0]

all_enables

biggest_size

150294

1

T1

221

T2

114

T3

130

values[0x1]

all_enables

biggest_size

136167

1

T1

213

T2

98

T3

116