Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	20554549	16816	0	0
attest_sw_binding_0_rd_A	20554549	2218	0	0
attest_sw_binding_1_rd_A	20554549	2304	0	0
attest_sw_binding_2_rd_A	20554549	1965	0	0
attest_sw_binding_3_rd_A	20554549	2115	0	0
attest_sw_binding_4_rd_A	20554549	2080	0	0
attest_sw_binding_5_rd_A	20554549	2096	0	0
attest_sw_binding_6_rd_A	20554549	2185	0	0
attest_sw_binding_7_rd_A	20554549	2067	0	0
intr_enable_rd_A	20554549	2805	0	0
key_version_rd_A	20554549	2036	0	0
max_creator_key_ver_regwen_rd_A	20554549	2049	0	0
max_owner_int_key_ver_regwen_rd_A	20554549	1951	0	0
max_owner_key_ver_regwen_rd_A	20554549	2114	0	0
reseed_interval_regwen_rd_A	20554549	2087	0	0
salt_0_rd_A	20554549	1978	0	0
salt_1_rd_A	20554549	2056	0	0
salt_2_rd_A	20554549	1978	0	0
salt_3_rd_A	20554549	2063	0	0
salt_4_rd_A	20554549	2109	0	0
salt_5_rd_A	20554549	2160	0	0
salt_6_rd_A	20554549	1989	0	0
salt_7_rd_A	20554549	2049	0	0
sealing_sw_binding_0_rd_A	20554549	2034	0	0
sealing_sw_binding_1_rd_A	20554549	2081	0	0
sealing_sw_binding_2_rd_A	20554549	1926	0	0
sealing_sw_binding_3_rd_A	20554549	1962	0	0
sealing_sw_binding_4_rd_A	20554549	2103	0	0
sealing_sw_binding_5_rd_A	20554549	2071	0	0
sealing_sw_binding_6_rd_A	20554549	2029	0	0
sealing_sw_binding_7_rd_A	20554549	2025	0	0
sideload_clear_rd_A	20554549	1944	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20554549	16816	0	0
T16	20850	1101	0	0
T17	2978	0	0	0
T18	11851	0	0	0
T48	62091	0	0	0
T59	6046	0	0	0
T70	0	626	0	0
T72	0	467	0	0
T74	0	425	0	0
T82	3513	0	0	0
T83	50979	0	0	0
T103	52527	0	0	0
T123	17337	0	0	0
T124	0	871	0	0
T126	0	757	0	0
T127	0	32	0	0
T129	0	111	0	0
T130	4865	0	0	0
T157	0	339	0	0
T176	0	54	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20554549	2218	0	0
T52	0	4	0	0
T99	25397	0	0	0
T127	29608	31	0	0
T128	1360	0	0	0
T153	0	98	0	0
T154	0	1	0	0
T177	0	22	0	0
T178	0	38	0	0
T179	0	5	0	0
T180	0	19	0	0
T181	0	74	0	0
T182	0	4	0	0
T183	10894	0	0	0
T184	2179	0	0	0
T185	11079	0	0	0
T186	7135	0	0	0
T187	2694	0	0	0
T188	3177	0	0	0
T189	4069	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20554549	2304	0	0
T52	0	11	0	0
T99	25397	0	0	0
T127	29608	30	0	0
T128	1360	0	0	0
T141	0	60	0	0
T153	0	81	0	0
T154	0	3	0	0
T177	0	23	0	0
T178	0	60	0	0
T179	0	20	0	0
T180	0	22	0	0
T181	0	35	0	0
T183	10894	0	0	0
T184	2179	0	0	0
T185	11079	0	0	0
T186	7135	0	0	0
T187	2694	0	0	0
T188	3177	0	0	0
T189	4069	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20554549	1965	0	0
T52	0	16	0	0
T99	25397	0	0	0
T127	29608	30	0	0
T128	1360	0	0	0
T153	0	78	0	0
T154	0	5	0	0
T177	0	43	0	0
T178	0	64	0	0
T179	0	7	0	0
T180	0	8	0	0
T181	0	33	0	0
T182	0	8	0	0
T183	10894	0	0	0
T184	2179	0	0	0
T185	11079	0	0	0
T186	7135	0	0	0
T187	2694	0	0	0
T188	3177	0	0	0
T189	4069	0	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20554549	2115	0	0
T52	0	10	0	0
T99	25397	0	0	0
T127	29608	32	0	0
T128	1360	0	0	0
T153	0	88	0	0
T154	0	5	0	0
T177	0	6	0	0
T178	0	78	0	0
T179	0	12	0	0
T180	0	18	0	0
T181	0	20	0	0
T182	0	9	0	0
T183	10894	0	0	0
T184	2179	0	0	0
T185	11079	0	0	0
T186	7135	0	0	0
T187	2694	0	0	0
T188	3177	0	0	0
T189	4069	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20554549	2080	0	0
T52	0	17	0	0
T99	25397	0	0	0
T127	29608	14	0	0
T128	1360	0	0	0
T141	0	83	0	0
T153	0	67	0	0
T154	0	1	0	0
T177	0	25	0	0
T178	0	55	0	0
T179	0	14	0	0
T180	0	19	0	0
T181	0	41	0	0
T183	10894	0	0	0
T184	2179	0	0	0
T185	11079	0	0	0
T186	7135	0	0	0
T187	2694	0	0	0
T188	3177	0	0	0
T189	4069	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20554549	2096	0	0
T52	0	21	0	0
T99	25397	0	0	0
T127	29608	41	0	0
T128	1360	0	0	0
T153	0	64	0	0
T154	0	2	0	0
T177	0	17	0	0
T178	0	72	0	0
T179	0	18	0	0
T180	0	21	0	0
T181	0	43	0	0
T182	0	8	0	0
T183	10894	0	0	0
T184	2179	0	0	0
T185	11079	0	0	0
T186	7135	0	0	0
T187	2694	0	0	0
T188	3177	0	0	0
T189	4069	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20554549	2185	0	0
T52	0	20	0	0
T99	25397	0	0	0
T127	29608	27	0	0
T128	1360	0	0	0
T153	0	80	0	0
T154	0	1	0	0
T177	0	22	0	0
T178	0	88	0	0
T179	0	2	0	0
T180	0	12	0	0
T181	0	55	0	0
T182	0	8	0	0
T183	10894	0	0	0
T184	2179	0	0	0
T185	11079	0	0	0
T186	7135	0	0	0
T187	2694	0	0	0
T188	3177	0	0	0
T189	4069	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20554549	2067	0	0
T52	0	10	0	0
T99	25397	0	0	0
T127	29608	37	0	0
T128	1360	0	0	0
T141	0	30	0	0
T153	0	87	0	0
T154	0	6	0	0
T177	0	19	0	0
T178	0	64	0	0
T179	0	20	0	0
T180	0	21	0	0
T181	0	30	0	0
T183	10894	0	0	0
T184	2179	0	0	0
T185	11079	0	0	0
T186	7135	0	0	0
T187	2694	0	0	0
T188	3177	0	0	0
T189	4069	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20554549	2805	0	0
T4	116828	11	0	0
T5	0	48	0	0
T15	19756	0	0	0
T16	20850	0	0	0
T17	2978	0	0	0
T18	11851	0	0	0
T48	62091	0	0	0
T52	0	43	0	0
T58	0	56	0	0
T59	6046	0	0	0
T75	0	20	0	0
T82	3513	0	0	0
T83	50979	0	0	0
T103	52527	0	0	0
T127	0	33	0	0
T190	0	64	0	0
T191	0	85	0	0
T192	0	12	0	0
T193	0	33	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20554549	2036	0	0
T52	0	4	0	0
T99	25397	0	0	0
T127	29608	32	0	0
T128	1360	0	0	0
T141	0	25	0	0
T153	0	88	0	0
T177	0	26	0	0
T178	0	66	0	0
T179	0	23	0	0
T180	0	17	0	0
T181	0	30	0	0
T182	0	7	0	0
T183	10894	0	0	0
T184	2179	0	0	0
T185	11079	0	0	0
T186	7135	0	0	0
T187	2694	0	0	0
T188	3177	0	0	0
T189	4069	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20554549	2049	0	0
T52	0	21	0	0
T99	25397	0	0	0
T127	29608	25	0	0
T128	1360	0	0	0
T153	0	73	0	0
T154	0	3	0	0
T177	0	24	0	0
T178	0	68	0	0
T179	0	17	0	0
T180	0	14	0	0
T181	0	38	0	0
T182	0	6	0	0
T183	10894	0	0	0
T184	2179	0	0	0
T185	11079	0	0	0
T186	7135	0	0	0
T187	2694	0	0	0
T188	3177	0	0	0
T189	4069	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20554549	1951	0	0
T52	0	7	0	0
T99	25397	0	0	0
T127	29608	25	0	0
T128	1360	0	0	0
T153	0	89	0	0
T154	0	3	0	0
T177	0	19	0	0
T178	0	78	0	0
T179	0	22	0	0
T180	0	26	0	0
T181	0	14	0	0
T182	0	3	0	0
T183	10894	0	0	0
T184	2179	0	0	0
T185	11079	0	0	0
T186	7135	0	0	0
T187	2694	0	0	0
T188	3177	0	0	0
T189	4069	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20554549	2114	0	0
T52	0	12	0	0
T99	25397	0	0	0
T127	29608	13	0	0
T128	1360	0	0	0
T153	0	81	0	0
T154	0	2	0	0
T177	0	4	0	0
T178	0	59	0	0
T179	0	11	0	0
T180	0	12	0	0
T181	0	26	0	0
T182	0	4	0	0
T183	10894	0	0	0
T184	2179	0	0	0
T185	11079	0	0	0
T186	7135	0	0	0
T187	2694	0	0	0
T188	3177	0	0	0
T189	4069	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20554549	2087	0	0
T52	0	15	0	0
T99	25397	0	0	0
T127	29608	10	0	0
T128	1360	0	0	0
T153	0	46	0	0
T154	0	7	0	0
T177	0	4	0	0
T178	0	67	0	0
T179	0	8	0	0
T180	0	13	0	0
T181	0	26	0	0
T182	0	2	0	0
T183	10894	0	0	0
T184	2179	0	0	0
T185	11079	0	0	0
T186	7135	0	0	0
T187	2694	0	0	0
T188	3177	0	0	0
T189	4069	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20554549	1978	0	0
T52	0	28	0	0
T99	25397	0	0	0
T127	29608	34	0	0
T128	1360	0	0	0
T153	0	81	0	0
T154	0	6	0	0
T177	0	10	0	0
T178	0	62	0	0
T179	0	8	0	0
T180	0	12	0	0
T181	0	30	0	0
T182	0	8	0	0
T183	10894	0	0	0
T184	2179	0	0	0
T185	11079	0	0	0
T186	7135	0	0	0
T187	2694	0	0	0
T188	3177	0	0	0
T189	4069	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20554549	2056	0	0
T52	0	9	0	0
T99	25397	0	0	0
T127	29608	32	0	0
T128	1360	0	0	0
T153	0	53	0	0
T154	0	1	0	0
T177	0	28	0	0
T178	0	55	0	0
T179	0	19	0	0
T180	0	11	0	0
T181	0	25	0	0
T182	0	3	0	0
T183	10894	0	0	0
T184	2179	0	0	0
T185	11079	0	0	0
T186	7135	0	0	0
T187	2694	0	0	0
T188	3177	0	0	0
T189	4069	0	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20554549	1978	0	0
T52	0	5	0	0
T99	25397	0	0	0
T127	29608	29	0	0
T128	1360	0	0	0
T153	0	71	0	0
T154	0	1	0	0
T177	0	19	0	0
T178	0	76	0	0
T179	0	6	0	0
T180	0	18	0	0
T181	0	33	0	0
T182	0	6	0	0
T183	10894	0	0	0
T184	2179	0	0	0
T185	11079	0	0	0
T186	7135	0	0	0
T187	2694	0	0	0
T188	3177	0	0	0
T189	4069	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20554549	2063	0	0
T52	0	22	0	0
T99	25397	0	0	0
T127	29608	37	0	0
T128	1360	0	0	0
T153	0	82	0	0
T154	0	1	0	0
T177	0	16	0	0
T178	0	90	0	0
T179	0	11	0	0
T180	0	20	0	0
T181	0	20	0	0
T182	0	4	0	0
T183	10894	0	0	0
T184	2179	0	0	0
T185	11079	0	0	0
T186	7135	0	0	0
T187	2694	0	0	0
T188	3177	0	0	0
T189	4069	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20554549	2109	0	0
T52	0	13	0	0
T99	25397	0	0	0
T127	29608	18	0	0
T128	1360	0	0	0
T153	0	73	0	0
T154	0	1	0	0
T177	0	9	0	0
T178	0	58	0	0
T179	0	2	0	0
T180	0	14	0	0
T181	0	46	0	0
T182	0	5	0	0
T183	10894	0	0	0
T184	2179	0	0	0
T185	11079	0	0	0
T186	7135	0	0	0
T187	2694	0	0	0
T188	3177	0	0	0
T189	4069	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20554549	2160	0	0
T52	0	14	0	0
T99	25397	0	0	0
T127	29608	26	0	0
T128	1360	0	0	0
T153	0	101	0	0
T154	0	6	0	0
T177	0	25	0	0
T178	0	61	0	0
T179	0	22	0	0
T180	0	17	0	0
T181	0	39	0	0
T182	0	1	0	0
T183	10894	0	0	0
T184	2179	0	0	0
T185	11079	0	0	0
T186	7135	0	0	0
T187	2694	0	0	0
T188	3177	0	0	0
T189	4069	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20554549	1989	0	0
T52	0	9	0	0
T99	25397	0	0	0
T127	29608	30	0	0
T128	1360	0	0	0
T141	0	27	0	0
T153	0	71	0	0
T154	0	4	0	0
T178	0	28	0	0
T179	0	7	0	0
T180	0	13	0	0
T181	0	32	0	0
T182	0	3	0	0
T183	10894	0	0	0
T184	2179	0	0	0
T185	11079	0	0	0
T186	7135	0	0	0
T187	2694	0	0	0
T188	3177	0	0	0
T189	4069	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20554549	2049	0	0
T52	0	22	0	0
T99	25397	0	0	0
T127	29608	26	0	0
T128	1360	0	0	0
T141	0	9	0	0
T153	0	80	0	0
T154	0	1	0	0
T177	0	10	0	0
T178	0	67	0	0
T179	0	14	0	0
T180	0	8	0	0
T181	0	50	0	0
T183	10894	0	0	0
T184	2179	0	0	0
T185	11079	0	0	0
T186	7135	0	0	0
T187	2694	0	0	0
T188	3177	0	0	0
T189	4069	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20554549	2034	0	0
T52	0	11	0	0
T99	25397	0	0	0
T127	29608	11	0	0
T128	1360	0	0	0
T153	0	94	0	0
T154	0	9	0	0
T177	0	12	0	0
T178	0	68	0	0
T179	0	12	0	0
T180	0	7	0	0
T181	0	32	0	0
T182	0	5	0	0
T183	10894	0	0	0
T184	2179	0	0	0
T185	11079	0	0	0
T186	7135	0	0	0
T187	2694	0	0	0
T188	3177	0	0	0
T189	4069	0	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20554549	2081	0	0
T52	0	12	0	0
T99	25397	0	0	0
T127	29608	20	0	0
T128	1360	0	0	0
T141	0	74	0	0
T153	0	72	0	0
T154	0	3	0	0
T177	0	25	0	0
T178	0	54	0	0
T179	0	13	0	0
T180	0	9	0	0
T181	0	53	0	0
T183	10894	0	0	0
T184	2179	0	0	0
T185	11079	0	0	0
T186	7135	0	0	0
T187	2694	0	0	0
T188	3177	0	0	0
T189	4069	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20554549	1926	0	0
T52	0	20	0	0
T99	25397	0	0	0
T127	29608	24	0	0
T128	1360	0	0	0
T153	0	88	0	0
T154	0	1	0	0
T177	0	16	0	0
T178	0	53	0	0
T179	0	6	0	0
T180	0	7	0	0
T181	0	38	0	0
T182	0	3	0	0
T183	10894	0	0	0
T184	2179	0	0	0
T185	11079	0	0	0
T186	7135	0	0	0
T187	2694	0	0	0
T188	3177	0	0	0
T189	4069	0	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20554549	1962	0	0
T52	0	28	0	0
T99	25397	0	0	0
T127	29608	16	0	0
T128	1360	0	0	0
T141	0	59	0	0
T153	0	71	0	0
T154	0	1	0	0
T177	0	5	0	0
T178	0	64	0	0
T179	0	32	0	0
T180	0	7	0	0
T181	0	26	0	0
T183	10894	0	0	0
T184	2179	0	0	0
T185	11079	0	0	0
T186	7135	0	0	0
T187	2694	0	0	0
T188	3177	0	0	0
T189	4069	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20554549	2103	0	0
T52	0	9	0	0
T99	25397	0	0	0
T127	29608	13	0	0
T128	1360	0	0	0
T153	0	92	0	0
T154	0	8	0	0
T177	0	9	0	0
T178	0	93	0	0
T179	0	36	0	0
T180	0	11	0	0
T181	0	26	0	0
T182	0	4	0	0
T183	10894	0	0	0
T184	2179	0	0	0
T185	11079	0	0	0
T186	7135	0	0	0
T187	2694	0	0	0
T188	3177	0	0	0
T189	4069	0	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20554549	2071	0	0
T52	0	24	0	0
T99	25397	0	0	0
T127	29608	23	0	0
T128	1360	0	0	0
T153	0	76	0	0
T154	0	6	0	0
T177	0	5	0	0
T178	0	50	0	0
T179	0	13	0	0
T180	0	19	0	0
T181	0	48	0	0
T182	0	4	0	0
T183	10894	0	0	0
T184	2179	0	0	0
T185	11079	0	0	0
T186	7135	0	0	0
T187	2694	0	0	0
T188	3177	0	0	0
T189	4069	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20554549	2029	0	0
T52	0	31	0	0
T99	25397	0	0	0
T127	29608	33	0	0
T128	1360	0	0	0
T153	0	96	0	0
T154	0	5	0	0
T177	0	10	0	0
T178	0	37	0	0
T179	0	23	0	0
T180	0	5	0	0
T181	0	18	0	0
T182	0	8	0	0
T183	10894	0	0	0
T184	2179	0	0	0
T185	11079	0	0	0
T186	7135	0	0	0
T187	2694	0	0	0
T188	3177	0	0	0
T189	4069	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20554549	2025	0	0
T52	0	14	0	0
T99	25397	0	0	0
T127	29608	27	0	0
T128	1360	0	0	0
T153	0	58	0	0
T154	0	1	0	0
T177	0	11	0	0
T178	0	62	0	0
T179	0	10	0	0
T180	0	23	0	0
T181	0	27	0	0
T182	0	6	0	0
T183	10894	0	0	0
T184	2179	0	0	0
T185	11079	0	0	0
T186	7135	0	0	0
T187	2694	0	0	0
T188	3177	0	0	0
T189	4069	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20554549	1944	0	0
T52	0	16	0	0
T99	25397	0	0	0
T127	29608	17	0	0
T128	1360	0	0	0
T153	0	68	0	0
T154	0	6	0	0
T177	0	14	0	0
T178	0	56	0	0
T179	0	22	0	0
T180	0	13	0	0
T181	0	38	0	0
T182	0	3	0	0
T183	10894	0	0	0
T184	2179	0	0	0
T185	11079	0	0	0
T186	7135	0	0	0
T187	2694	0	0	0
T188	3177	0	0	0
T189	4069	0	0	0