Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3121952	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

637136

1

T1

280

T2

140

T3

163

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3329744	1			T1	274		T2	226		T3	1413
values[0x0]	213042	1			T1	103		T2	64		T3	40
values[0x1]	216302	1			T1	112		T2	69		T3	44

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2141580	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1617508

1

T1

336

T2

207

T3

556

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9862	1			T2	1		T3	3		T4	46
valid_sources[0x01]	10991	1			T3	6		T4	61		T5	10
valid_sources[0x02]	57631	1			T1	1		T2	2		T3	13
valid_sources[0x03]	16385	1			T1	3		T2	1		T3	7
valid_sources[0x04]	10080	1			T1	1		T2	2		T3	4
valid_sources[0x05]	10983	1			T1	2		T2	1		T3	4
valid_sources[0x06]	18792	1			T1	1		T3	7		T4	35
valid_sources[0x07]	9618	1			T1	2		T3	9		T4	53
valid_sources[0x08]	10197	1			T1	3		T3	11		T4	54
valid_sources[0x09]	26923	1			T3	2		T4	48		T5	18
valid_sources[0x0a]	11936	1			T1	4		T2	1		T3	4
valid_sources[0x0b]	10681	1			T1	1		T2	1		T3	6
valid_sources[0x0c]	10412	1			T1	2		T2	3		T3	4
valid_sources[0x0d]	10132	1			T1	4		T2	5		T3	3
valid_sources[0x0e]	42656	1			T1	1		T2	3		T3	4
valid_sources[0x0f]	12172	1			T1	5		T2	1		T3	6
valid_sources[0x10]	11417	1			T2	3		T3	8		T4	68
valid_sources[0x11]	10815	1			T1	2		T2	2		T3	4
valid_sources[0x12]	10895	1			T1	2		T2	2		T3	4
valid_sources[0x13]	10125	1			T1	1		T2	2		T3	2
valid_sources[0x14]	12020	1			T1	3		T2	3		T3	7
valid_sources[0x15]	14679	1			T1	1		T2	1		T3	8
valid_sources[0x16]	53759	1			T1	1		T2	4		T3	4
valid_sources[0x17]	12865	1			T1	3		T3	6		T4	45
valid_sources[0x18]	10286	1			T1	1		T3	2		T4	57
valid_sources[0x19]	11084	1			T2	1		T3	3		T4	70
valid_sources[0x1a]	10196	1			T1	6		T2	3		T3	7
valid_sources[0x1b]	11526	1			T1	1		T2	3		T3	4
valid_sources[0x1c]	11029	1			T1	1		T2	2		T3	9
valid_sources[0x1d]	10225	1			T2	1		T3	2		T4	61
valid_sources[0x1e]	11615	1			T1	1		T2	1		T3	5
valid_sources[0x1f]	15872	1			T1	1		T3	4		T4	58
valid_sources[0x20]	12302	1			T1	5		T3	8		T4	48
valid_sources[0x21]	13828	1			T1	1		T3	4		T4	47
valid_sources[0x22]	10647	1			T1	1		T2	3		T3	5
valid_sources[0x23]	12335	1			T1	2		T2	1		T3	7
valid_sources[0x24]	10132	1			T1	1		T2	2		T3	6
valid_sources[0x25]	33631	1			T1	1		T3	8		T4	46
valid_sources[0x26]	10306	1			T1	1		T2	1		T3	7
valid_sources[0x27]	28481	1			T1	3		T3	7		T4	44
valid_sources[0x28]	10131	1			T1	2		T2	1		T3	6
valid_sources[0x29]	11116	1			T2	2		T3	8		T4	54
valid_sources[0x2a]	9810	1			T1	2		T3	5		T4	50
valid_sources[0x2b]	10284	1			T1	1		T2	1		T3	11
valid_sources[0x2c]	11078	1			T1	3		T3	9		T4	59
valid_sources[0x2d]	10565	1			T1	1		T2	1		T3	7
valid_sources[0x2e]	10504	1			T1	2		T2	3		T3	5
valid_sources[0x2f]	27043	1			T1	2		T2	3		T3	8
valid_sources[0x30]	11052	1			T2	1		T3	6		T4	56
valid_sources[0x31]	27608	1			T2	2		T3	3		T4	44
valid_sources[0x32]	13564	1			T2	1		T3	4		T4	36
valid_sources[0x33]	10470	1			T1	2		T2	3		T3	3
valid_sources[0x34]	10309	1			T1	2		T3	5		T4	47
valid_sources[0x35]	18524	1			T1	2		T2	5		T3	11
valid_sources[0x36]	14839	1			T2	2		T3	7		T4	52
valid_sources[0x37]	10494	1			T1	1		T3	3		T4	53
valid_sources[0x38]	10144	1			T1	2		T2	1		T3	6
valid_sources[0x39]	13146	1			T1	4		T2	2		T3	6
valid_sources[0x3a]	11622	1			T1	2		T3	5		T4	57
valid_sources[0x3b]	11408	1			T1	1		T2	5		T3	7
valid_sources[0x3c]	11562	1			T1	3		T3	11		T4	51
valid_sources[0x3d]	11226	1			T1	3		T2	2		T3	4
valid_sources[0x3e]	20565	1			T1	2		T3	5		T4	59
valid_sources[0x3f]	10546	1			T1	3		T3	2		T4	50
valid_sources[0x40]	10351	1			T1	1		T2	1		T3	4
valid_sources[0x41]	13007	1			T1	2		T3	1		T4	55
valid_sources[0x42]	11603	1			T1	1		T3	5		T4	51
valid_sources[0x43]	10910	1			T1	3		T2	2		T3	8
valid_sources[0x44]	11413	1			T1	3		T2	2		T3	5
valid_sources[0x45]	10035	1			T1	4		T2	1		T3	6
valid_sources[0x46]	24751	1			T1	3		T2	3		T3	4
valid_sources[0x47]	13167	1			T1	1		T2	1		T3	5
valid_sources[0x48]	11943	1			T1	3		T3	9		T4	44
valid_sources[0x49]	369158	1			T1	2		T3	10		T4	53
valid_sources[0x4a]	11988	1			T1	4		T2	3		T3	7
valid_sources[0x4b]	10340	1			T1	1		T2	3		T3	5
valid_sources[0x4c]	11576	1			T1	1		T2	1		T3	6
valid_sources[0x4d]	11929	1			T1	2		T2	1		T3	8
valid_sources[0x4e]	11546	1			T1	1		T2	2		T3	7
valid_sources[0x4f]	10635	1			T1	2		T2	4		T3	5
valid_sources[0x50]	10702	1			T1	3		T2	3		T3	5
valid_sources[0x51]	10726	1			T1	2		T2	1		T3	2
valid_sources[0x52]	9868	1			T1	1		T2	2		T3	9
valid_sources[0x53]	9925	1			T1	4		T3	8		T4	43
valid_sources[0x54]	10140	1			T1	2		T2	1		T3	6
valid_sources[0x55]	10269	1			T1	3		T2	2		T3	9
valid_sources[0x56]	10073	1			T1	5		T2	1		T3	3
valid_sources[0x57]	13856	1			T1	3		T2	2		T3	5
valid_sources[0x58]	11274	1			T1	2		T2	3		T3	6
valid_sources[0x59]	13464	1			T1	2		T2	2		T3	5
valid_sources[0x5a]	10513	1			T2	1		T3	5		T4	60
valid_sources[0x5b]	10464	1			T2	1		T3	4		T4	64
valid_sources[0x5c]	10701	1			T2	4		T3	2		T4	69
valid_sources[0x5d]	12100	1			T1	3		T3	3		T4	31
valid_sources[0x5e]	10030	1			T1	3		T2	1		T3	3
valid_sources[0x5f]	10102	1			T1	4		T2	2		T3	9
valid_sources[0x60]	10138	1			T1	1		T2	3		T3	5
valid_sources[0x61]	10001	1			T1	2		T2	1		T3	3
valid_sources[0x62]	12809	1			T1	3		T2	2		T3	7
valid_sources[0x63]	15992	1			T1	3		T2	1		T3	6
valid_sources[0x64]	11439	1			T1	2		T2	4		T3	6
valid_sources[0x65]	11811	1			T1	2		T2	1		T3	5
valid_sources[0x66]	10737	1			T1	1		T3	6		T4	58
valid_sources[0x67]	12297	1			T1	1		T3	5		T4	49
valid_sources[0x68]	9912	1			T1	2		T3	4		T4	61
valid_sources[0x69]	10863	1			T1	2		T2	2		T3	13
valid_sources[0x6a]	10716	1			T1	3		T2	2		T3	7
valid_sources[0x6b]	9868	1			T1	2		T2	2		T3	7
valid_sources[0x6c]	13780	1			T1	1		T2	3		T3	2
valid_sources[0x6d]	14552	1			T1	4		T2	1		T3	2
valid_sources[0x6e]	15361	1			T1	1		T3	2		T4	47
valid_sources[0x6f]	10740	1			T3	2		T4	96		T5	20
valid_sources[0x70]	10245	1			T2	1		T3	2		T4	80
valid_sources[0x71]	11908	1			T1	1		T3	5		T4	40
valid_sources[0x72]	14300	1			T2	2		T3	8		T4	65
valid_sources[0x73]	11195	1			T1	1		T2	1		T3	6
valid_sources[0x74]	10250	1			T1	5		T3	6		T4	56
valid_sources[0x75]	10864	1			T1	1		T2	1		T3	4
valid_sources[0x76]	40912	1			T1	2		T3	4		T4	41
valid_sources[0x77]	10228	1			T1	2		T2	2		T3	6
valid_sources[0x78]	11922	1			T1	2		T3	5		T4	53
valid_sources[0x79]	14939	1			T3	5		T4	55		T5	21
valid_sources[0x7a]	9901	1			T1	3		T2	2		T3	12
valid_sources[0x7b]	9946	1			T1	4		T2	1		T3	4
valid_sources[0x7c]	22788	1			T2	1		T3	7		T4	66
valid_sources[0x7d]	11471	1			T1	1		T2	5		T3	7
valid_sources[0x7e]	11440	1			T2	1		T3	6		T4	58
valid_sources[0x7f]	9823	1			T3	15		T4	52		T5	32
valid_sources[0x80]	9435	1			T1	2		T2	1		T3	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

343409

1

T1

117

T2

51

T3

134

values[0x0]

all_enables

biggest_size

154668

1

T1

77

T2

50

T3

16

values[0x1]

all_enables

biggest_size

139059

1

T1

86

T2

39

T3

13