Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.94	96.00	97.81	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	24071310	18114	0	0
attest_sw_binding_0_rd_A	24071310	4032	0	0
attest_sw_binding_1_rd_A	24071310	3884	0	0
attest_sw_binding_2_rd_A	24071310	3710	0	0
attest_sw_binding_3_rd_A	24071310	4011	0	0
attest_sw_binding_4_rd_A	24071310	3934	0	0
attest_sw_binding_5_rd_A	24071310	3793	0	0
attest_sw_binding_6_rd_A	24071310	3831	0	0
attest_sw_binding_7_rd_A	24071310	3898	0	0
intr_enable_rd_A	24071310	4351	0	0
key_version_rd_A	24071310	3957	0	0
max_creator_key_ver_regwen_rd_A	24071310	3879	0	0
max_owner_int_key_ver_regwen_rd_A	24071310	3700	0	0
max_owner_key_ver_regwen_rd_A	24071310	3721	0	0
reseed_interval_regwen_rd_A	24071310	3763	0	0
salt_0_rd_A	24071310	3791	0	0
salt_1_rd_A	24071310	3789	0	0
salt_2_rd_A	24071310	3795	0	0
salt_3_rd_A	24071310	3904	0	0
salt_4_rd_A	24071310	4009	0	0
salt_5_rd_A	24071310	3687	0	0
salt_6_rd_A	24071310	3889	0	0
salt_7_rd_A	24071310	3715	0	0
sealing_sw_binding_0_rd_A	24071310	3546	0	0
sealing_sw_binding_1_rd_A	24071310	3874	0	0
sealing_sw_binding_2_rd_A	24071310	3772	0	0
sealing_sw_binding_3_rd_A	24071310	3795	0	0
sealing_sw_binding_4_rd_A	24071310	3958	0	0
sealing_sw_binding_5_rd_A	24071310	3665	0	0
sealing_sw_binding_6_rd_A	24071310	3817	0	0
sealing_sw_binding_7_rd_A	24071310	3745	0	0
sideload_clear_rd_A	24071310	3824	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24071310	18114	0	0
T5	66563	99	0	0
T12	27541	0	0	0
T13	1925	0	0	0
T14	4442	0	0	0
T15	4369	0	0	0
T16	7452	0	0	0
T39	4620	0	0	0
T40	0	331	0	0
T48	0	939	0	0
T57	0	271	0	0
T66	0	1356	0	0
T84	8752	0	0	0
T85	2129	0	0	0
T88	1051	0	0	0
T108	0	284	0	0
T135	0	365	0	0
T136	0	17	0	0
T137	0	1005	0	0
T138	0	167	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24071310	4032	0	0
T5	66563	68	0	0
T12	27541	0	0	0
T13	1925	0	0	0
T14	4442	0	0	0
T15	4369	0	0	0
T16	7452	0	0	0
T39	4620	0	0	0
T47	0	16	0	0
T84	8752	0	0	0
T85	2129	0	0	0
T88	1051	0	0	0
T131	0	227	0	0
T138	0	65	0	0
T157	0	5	0	0
T184	0	22	0	0
T185	0	35	0	0
T186	0	76	0	0
T187	0	8	0	0
T188	0	28	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24071310	3884	0	0
T5	66563	56	0	0
T12	27541	0	0	0
T13	1925	0	0	0
T14	4442	0	0	0
T15	4369	0	0	0
T16	7452	0	0	0
T39	4620	0	0	0
T47	0	33	0	0
T84	8752	0	0	0
T85	2129	0	0	0
T88	1051	0	0	0
T131	0	251	0	0
T138	0	58	0	0
T157	0	5	0	0
T184	0	41	0	0
T185	0	24	0	0
T186	0	56	0	0
T187	0	6	0	0
T188	0	18	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24071310	3710	0	0
T5	66563	54	0	0
T12	27541	0	0	0
T13	1925	0	0	0
T14	4442	0	0	0
T15	4369	0	0	0
T16	7452	0	0	0
T39	4620	0	0	0
T47	0	36	0	0
T84	8752	0	0	0
T85	2129	0	0	0
T88	1051	0	0	0
T131	0	193	0	0
T138	0	54	0	0
T157	0	2	0	0
T184	0	14	0	0
T185	0	17	0	0
T186	0	66	0	0
T187	0	9	0	0
T189	0	5	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24071310	4011	0	0
T5	66563	51	0	0
T12	27541	0	0	0
T13	1925	0	0	0
T14	4442	0	0	0
T15	4369	0	0	0
T16	7452	0	0	0
T39	4620	0	0	0
T47	0	40	0	0
T84	8752	0	0	0
T85	2129	0	0	0
T88	1051	0	0	0
T131	0	238	0	0
T138	0	78	0	0
T157	0	5	0	0
T184	0	26	0	0
T185	0	50	0	0
T186	0	67	0	0
T187	0	18	0	0
T188	0	13	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24071310	3934	0	0
T5	66563	68	0	0
T12	27541	0	0	0
T13	1925	0	0	0
T14	4442	0	0	0
T15	4369	0	0	0
T16	7452	0	0	0
T39	4620	0	0	0
T47	0	38	0	0
T84	8752	0	0	0
T85	2129	0	0	0
T88	1051	0	0	0
T131	0	225	0	0
T138	0	40	0	0
T157	0	1	0	0
T184	0	17	0	0
T185	0	43	0	0
T186	0	64	0	0
T187	0	5	0	0
T189	0	9	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24071310	3793	0	0
T5	66563	45	0	0
T12	27541	0	0	0
T13	1925	0	0	0
T14	4442	0	0	0
T15	4369	0	0	0
T16	7452	0	0	0
T39	4620	0	0	0
T47	0	30	0	0
T84	8752	0	0	0
T85	2129	0	0	0
T88	1051	0	0	0
T131	0	244	0	0
T138	0	49	0	0
T157	0	1	0	0
T184	0	37	0	0
T185	0	31	0	0
T186	0	80	0	0
T187	0	9	0	0
T188	0	14	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24071310	3831	0	0
T5	66563	75	0	0
T12	27541	0	0	0
T13	1925	0	0	0
T14	4442	0	0	0
T15	4369	0	0	0
T16	7452	0	0	0
T39	4620	0	0	0
T47	0	21	0	0
T84	8752	0	0	0
T85	2129	0	0	0
T88	1051	0	0	0
T131	0	230	0	0
T138	0	50	0	0
T157	0	8	0	0
T184	0	28	0	0
T185	0	24	0	0
T186	0	51	0	0
T187	0	18	0	0
T189	0	2	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24071310	3898	0	0
T5	66563	71	0	0
T12	27541	0	0	0
T13	1925	0	0	0
T14	4442	0	0	0
T15	4369	0	0	0
T16	7452	0	0	0
T39	4620	0	0	0
T47	0	24	0	0
T84	8752	0	0	0
T85	2129	0	0	0
T88	1051	0	0	0
T131	0	232	0	0
T138	0	57	0	0
T157	0	6	0	0
T184	0	27	0	0
T185	0	27	0	0
T186	0	61	0	0
T187	0	1	0	0
T188	0	18	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24071310	4351	0	0
T5	66563	111	0	0
T12	27541	0	0	0
T13	1925	0	0	0
T14	4442	0	0	0
T15	4369	0	0	0
T16	7452	0	0	0
T39	4620	0	0	0
T47	0	20	0	0
T74	0	12	0	0
T84	8752	0	0	0
T85	2129	0	0	0
T88	1051	0	0	0
T138	0	67	0	0
T184	0	34	0	0
T185	0	29	0	0
T186	0	69	0	0
T190	0	47	0	0
T191	0	9	0	0
T192	0	7	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24071310	3957	0	0
T5	66563	39	0	0
T12	27541	0	0	0
T13	1925	0	0	0
T14	4442	0	0	0
T15	4369	0	0	0
T16	7452	0	0	0
T39	4620	0	0	0
T47	0	18	0	0
T84	8752	0	0	0
T85	2129	0	0	0
T88	1051	0	0	0
T131	0	205	0	0
T138	0	35	0	0
T157	0	4	0	0
T184	0	35	0	0
T185	0	46	0	0
T186	0	50	0	0
T187	0	1	0	0
T189	0	8	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24071310	3879	0	0
T5	66563	93	0	0
T12	27541	0	0	0
T13	1925	0	0	0
T14	4442	0	0	0
T15	4369	0	0	0
T16	7452	0	0	0
T39	4620	0	0	0
T47	0	35	0	0
T84	8752	0	0	0
T85	2129	0	0	0
T88	1051	0	0	0
T131	0	234	0	0
T138	0	41	0	0
T157	0	6	0	0
T184	0	51	0	0
T185	0	16	0	0
T186	0	76	0	0
T187	0	14	0	0
T189	0	6	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24071310	3700	0	0
T5	66563	22	0	0
T12	27541	0	0	0
T13	1925	0	0	0
T14	4442	0	0	0
T15	4369	0	0	0
T16	7452	0	0	0
T39	4620	0	0	0
T47	0	39	0	0
T84	8752	0	0	0
T85	2129	0	0	0
T88	1051	0	0	0
T131	0	257	0	0
T138	0	38	0	0
T157	0	1	0	0
T184	0	23	0	0
T185	0	17	0	0
T186	0	55	0	0
T187	0	8	0	0
T189	0	13	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24071310	3721	0	0
T5	66563	36	0	0
T12	27541	0	0	0
T13	1925	0	0	0
T14	4442	0	0	0
T15	4369	0	0	0
T16	7452	0	0	0
T39	4620	0	0	0
T47	0	47	0	0
T84	8752	0	0	0
T85	2129	0	0	0
T88	1051	0	0	0
T131	0	239	0	0
T138	0	51	0	0
T157	0	5	0	0
T184	0	31	0	0
T185	0	16	0	0
T186	0	89	0	0
T187	0	8	0	0
T189	0	1	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24071310	3763	0	0
T5	66563	54	0	0
T12	27541	0	0	0
T13	1925	0	0	0
T14	4442	0	0	0
T15	4369	0	0	0
T16	7452	0	0	0
T39	4620	0	0	0
T47	0	27	0	0
T84	8752	0	0	0
T85	2129	0	0	0
T88	1051	0	0	0
T131	0	190	0	0
T138	0	35	0	0
T157	0	1	0	0
T184	0	24	0	0
T185	0	24	0	0
T186	0	61	0	0
T187	0	4	0	0
T188	0	17	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24071310	3791	0	0
T5	66563	54	0	0
T12	27541	0	0	0
T13	1925	0	0	0
T14	4442	0	0	0
T15	4369	0	0	0
T16	7452	0	0	0
T39	4620	0	0	0
T47	0	18	0	0
T84	8752	0	0	0
T85	2129	0	0	0
T88	1051	0	0	0
T131	0	165	0	0
T138	0	60	0	0
T157	0	4	0	0
T184	0	30	0	0
T185	0	18	0	0
T186	0	47	0	0
T188	0	13	0	0
T189	0	5	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24071310	3789	0	0
T5	66563	64	0	0
T12	27541	0	0	0
T13	1925	0	0	0
T14	4442	0	0	0
T15	4369	0	0	0
T16	7452	0	0	0
T39	4620	0	0	0
T47	0	19	0	0
T84	8752	0	0	0
T85	2129	0	0	0
T88	1051	0	0	0
T131	0	192	0	0
T138	0	38	0	0
T157	0	2	0	0
T184	0	33	0	0
T185	0	24	0	0
T186	0	66	0	0
T187	0	7	0	0
T189	0	5	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24071310	3795	0	0
T5	66563	40	0	0
T12	27541	0	0	0
T13	1925	0	0	0
T14	4442	0	0	0
T15	4369	0	0	0
T16	7452	0	0	0
T39	4620	0	0	0
T47	0	35	0	0
T84	8752	0	0	0
T85	2129	0	0	0
T88	1051	0	0	0
T131	0	184	0	0
T138	0	53	0	0
T157	0	8	0	0
T184	0	34	0	0
T185	0	22	0	0
T186	0	67	0	0
T187	0	6	0	0
T188	0	27	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24071310	3904	0	0
T5	66563	51	0	0
T12	27541	0	0	0
T13	1925	0	0	0
T14	4442	0	0	0
T15	4369	0	0	0
T16	7452	0	0	0
T39	4620	0	0	0
T47	0	42	0	0
T84	8752	0	0	0
T85	2129	0	0	0
T88	1051	0	0	0
T131	0	237	0	0
T138	0	34	0	0
T157	0	4	0	0
T179	0	37	0	0
T184	0	31	0	0
T185	0	33	0	0
T186	0	63	0	0
T188	0	13	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24071310	4009	0	0
T5	66563	39	0	0
T12	27541	0	0	0
T13	1925	0	0	0
T14	4442	0	0	0
T15	4369	0	0	0
T16	7452	0	0	0
T39	4620	0	0	0
T47	0	23	0	0
T84	8752	0	0	0
T85	2129	0	0	0
T88	1051	0	0	0
T131	0	221	0	0
T133	0	118	0	0
T138	0	35	0	0
T179	0	49	0	0
T184	0	22	0	0
T185	0	46	0	0
T186	0	79	0	0
T188	0	25	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24071310	3687	0	0
T5	66563	59	0	0
T12	27541	0	0	0
T13	1925	0	0	0
T14	4442	0	0	0
T15	4369	0	0	0
T16	7452	0	0	0
T39	4620	0	0	0
T47	0	37	0	0
T84	8752	0	0	0
T85	2129	0	0	0
T88	1051	0	0	0
T131	0	209	0	0
T138	0	21	0	0
T157	0	4	0	0
T184	0	43	0	0
T185	0	21	0	0
T186	0	81	0	0
T187	0	5	0	0
T188	0	5	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24071310	3889	0	0
T5	66563	63	0	0
T12	27541	0	0	0
T13	1925	0	0	0
T14	4442	0	0	0
T15	4369	0	0	0
T16	7452	0	0	0
T39	4620	0	0	0
T47	0	44	0	0
T84	8752	0	0	0
T85	2129	0	0	0
T88	1051	0	0	0
T131	0	207	0	0
T138	0	40	0	0
T157	0	6	0	0
T184	0	26	0	0
T185	0	38	0	0
T186	0	59	0	0
T187	0	10	0	0
T188	0	10	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24071310	3715	0	0
T5	66563	39	0	0
T12	27541	0	0	0
T13	1925	0	0	0
T14	4442	0	0	0
T15	4369	0	0	0
T16	7452	0	0	0
T39	4620	0	0	0
T47	0	31	0	0
T84	8752	0	0	0
T85	2129	0	0	0
T88	1051	0	0	0
T131	0	218	0	0
T138	0	57	0	0
T184	0	30	0	0
T185	0	9	0	0
T186	0	36	0	0
T187	0	9	0	0
T188	0	11	0	0
T189	0	6	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24071310	3546	0	0
T5	66563	30	0	0
T12	27541	0	0	0
T13	1925	0	0	0
T14	4442	0	0	0
T15	4369	0	0	0
T16	7452	0	0	0
T39	4620	0	0	0
T47	0	17	0	0
T84	8752	0	0	0
T85	2129	0	0	0
T88	1051	0	0	0
T131	0	213	0	0
T138	0	67	0	0
T157	0	6	0	0
T184	0	38	0	0
T185	0	34	0	0
T186	0	49	0	0
T187	0	15	0	0
T188	0	23	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24071310	3874	0	0
T5	66563	57	0	0
T12	27541	0	0	0
T13	1925	0	0	0
T14	4442	0	0	0
T15	4369	0	0	0
T16	7452	0	0	0
T39	4620	0	0	0
T47	0	37	0	0
T84	8752	0	0	0
T85	2129	0	0	0
T88	1051	0	0	0
T131	0	242	0	0
T138	0	59	0	0
T157	0	6	0	0
T184	0	25	0	0
T185	0	36	0	0
T186	0	62	0	0
T187	0	13	0	0
T189	0	6	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24071310	3772	0	0
T5	66563	41	0	0
T12	27541	0	0	0
T13	1925	0	0	0
T14	4442	0	0	0
T15	4369	0	0	0
T16	7452	0	0	0
T39	4620	0	0	0
T47	0	50	0	0
T84	8752	0	0	0
T85	2129	0	0	0
T88	1051	0	0	0
T131	0	194	0	0
T138	0	74	0	0
T157	0	5	0	0
T184	0	47	0	0
T185	0	29	0	0
T186	0	78	0	0
T187	0	7	0	0
T188	0	6	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24071310	3795	0	0
T5	66563	52	0	0
T12	27541	0	0	0
T13	1925	0	0	0
T14	4442	0	0	0
T15	4369	0	0	0
T16	7452	0	0	0
T39	4620	0	0	0
T47	0	35	0	0
T84	8752	0	0	0
T85	2129	0	0	0
T88	1051	0	0	0
T131	0	215	0	0
T138	0	53	0	0
T184	0	29	0	0
T185	0	37	0	0
T186	0	62	0	0
T187	0	18	0	0
T188	0	26	0	0
T189	0	6	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24071310	3958	0	0
T5	66563	42	0	0
T12	27541	0	0	0
T13	1925	0	0	0
T14	4442	0	0	0
T15	4369	0	0	0
T16	7452	0	0	0
T39	4620	0	0	0
T47	0	39	0	0
T84	8752	0	0	0
T85	2129	0	0	0
T88	1051	0	0	0
T131	0	259	0	0
T138	0	70	0	0
T157	0	1	0	0
T184	0	43	0	0
T185	0	36	0	0
T186	0	58	0	0
T187	0	12	0	0
T188	0	11	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24071310	3665	0	0
T5	66563	63	0	0
T12	27541	0	0	0
T13	1925	0	0	0
T14	4442	0	0	0
T15	4369	0	0	0
T16	7452	0	0	0
T39	4620	0	0	0
T47	0	32	0	0
T84	8752	0	0	0
T85	2129	0	0	0
T88	1051	0	0	0
T131	0	271	0	0
T138	0	33	0	0
T157	0	6	0	0
T184	0	22	0	0
T185	0	30	0	0
T186	0	35	0	0
T187	0	19	0	0
T188	0	9	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24071310	3817	0	0
T5	66563	56	0	0
T12	27541	0	0	0
T13	1925	0	0	0
T14	4442	0	0	0
T15	4369	0	0	0
T16	7452	0	0	0
T39	4620	0	0	0
T47	0	21	0	0
T84	8752	0	0	0
T85	2129	0	0	0
T88	1051	0	0	0
T131	0	227	0	0
T138	0	49	0	0
T157	0	7	0	0
T184	0	37	0	0
T185	0	31	0	0
T186	0	67	0	0
T187	0	1	0	0
T189	0	11	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24071310	3745	0	0
T5	66563	42	0	0
T12	27541	0	0	0
T13	1925	0	0	0
T14	4442	0	0	0
T15	4369	0	0	0
T16	7452	0	0	0
T39	4620	0	0	0
T47	0	35	0	0
T84	8752	0	0	0
T85	2129	0	0	0
T88	1051	0	0	0
T131	0	236	0	0
T138	0	59	0	0
T157	0	8	0	0
T184	0	16	0	0
T185	0	40	0	0
T186	0	68	0	0
T187	0	11	0	0
T188	0	27	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24071310	3824	0	0
T5	66563	38	0	0
T12	27541	0	0	0
T13	1925	0	0	0
T14	4442	0	0	0
T15	4369	0	0	0
T16	7452	0	0	0
T39	4620	0	0	0
T47	0	35	0	0
T84	8752	0	0	0
T85	2129	0	0	0
T88	1051	0	0	0
T131	0	286	0	0
T138	0	27	0	0
T157	0	3	0	0
T184	0	20	0	0
T185	0	41	0	0
T186	0	57	0	0
T187	0	12	0	0
T188	0	7	0	0