Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2970436	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

592400

1

T1

326

T2

201

T3

287

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3158627	1			T1	333		T2	333		T3	714
values[0x0]	200221	1			T1	149		T2	66		T3	125
values[0x1]	203988	1			T1	163		T2	59		T3	101

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2037274	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1525562

1

T1

394

T2

267

T3

458

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11642	1			T2	2		T14	5		T15	5
valid_sources[0x01]	10765	1			T2	1		T3	2		T4	1
valid_sources[0x02]	11510	1			T2	3		T3	4		T13	4
valid_sources[0x03]	10666	1			T2	1		T13	9		T14	7
valid_sources[0x04]	13994	1			T2	1		T3	5		T4	1
valid_sources[0x05]	10969	1			T2	1		T3	1		T12	1
valid_sources[0x06]	11649	1			T2	1		T4	1		T12	3
valid_sources[0x07]	12225	1			T2	2		T12	8		T13	3
valid_sources[0x08]	17272	1			T3	15		T4	2		T13	7
valid_sources[0x09]	21251	1			T2	1		T4	1		T13	7
valid_sources[0x0a]	11359	1			T2	4		T4	1		T13	3
valid_sources[0x0b]	25151	1			T2	2		T3	7		T4	4
valid_sources[0x0c]	15406	1			T2	3		T3	1		T4	1
valid_sources[0x0d]	11771	1			T2	1		T4	1		T13	1
valid_sources[0x0e]	16702	1			T2	1		T3	6		T4	2
valid_sources[0x0f]	16172	1			T12	12		T13	2		T14	1
valid_sources[0x10]	17256	1			T2	4		T3	2		T4	1
valid_sources[0x11]	12241	1			T2	3		T3	6		T12	1
valid_sources[0x12]	12708	1			T2	2		T3	6		T4	3
valid_sources[0x13]	10508	1			T4	1		T12	1		T13	2
valid_sources[0x14]	14885	1			T2	2		T12	1		T13	4
valid_sources[0x15]	23165	1			T2	2		T4	1		T13	8
valid_sources[0x16]	13996	1			T2	2		T13	2		T17	12
valid_sources[0x17]	10684	1			T2	3		T3	5		T12	2
valid_sources[0x18]	14352	1			T2	4		T13	8		T14	5
valid_sources[0x19]	10898	1			T2	1		T3	5		T4	1
valid_sources[0x1a]	15182	1			T2	2		T4	1		T13	2
valid_sources[0x1b]	13130	1			T2	2		T3	11		T4	1
valid_sources[0x1c]	10897	1			T2	3		T4	1		T13	6
valid_sources[0x1d]	16806	1			T2	2		T4	3		T13	2
valid_sources[0x1e]	11224	1			T3	15		T4	4		T13	5
valid_sources[0x1f]	11256	1			T2	1		T3	5		T4	1
valid_sources[0x20]	11805	1			T2	4		T3	2		T13	2
valid_sources[0x21]	11181	1			T2	2		T3	11		T4	2
valid_sources[0x22]	10941	1			T2	2		T3	3		T12	1
valid_sources[0x23]	13494	1			T2	2		T3	4		T4	1
valid_sources[0x24]	14994	1			T2	1		T13	3		T14	1
valid_sources[0x25]	13379	1			T2	2		T4	1		T13	4
valid_sources[0x26]	10891	1			T2	1		T4	2		T13	4
valid_sources[0x27]	12703	1			T2	2		T4	2		T13	1
valid_sources[0x28]	10065	1			T2	1		T3	9		T12	11
valid_sources[0x29]	11539	1			T2	4		T3	1		T4	2
valid_sources[0x2a]	10694	1			T2	1		T4	1		T13	7
valid_sources[0x2b]	11661	1			T2	3		T3	10		T4	1
valid_sources[0x2c]	12786	1			T2	3		T3	6		T12	1
valid_sources[0x2d]	11055	1			T2	1		T3	14		T13	5
valid_sources[0x2e]	16098	1			T1	645		T2	1		T4	1
valid_sources[0x2f]	10385	1			T2	1		T4	1		T13	15
valid_sources[0x30]	10570	1			T2	1		T4	1		T13	2
valid_sources[0x31]	11568	1			T2	2		T3	7		T13	2
valid_sources[0x32]	12111	1			T2	1		T3	2		T13	3
valid_sources[0x33]	10966	1			T2	1		T3	13		T4	1
valid_sources[0x34]	19475	1			T2	2		T4	3		T13	6
valid_sources[0x35]	67386	1			T2	5		T3	19		T13	5
valid_sources[0x36]	11920	1			T2	3		T4	1		T13	4
valid_sources[0x37]	10626	1			T2	4		T3	11		T13	5
valid_sources[0x38]	15062	1			T2	4		T3	6		T13	6
valid_sources[0x39]	24634	1			T2	3		T4	2		T12	1
valid_sources[0x3a]	12560	1			T2	1		T12	2		T13	5
valid_sources[0x3b]	10446	1			T2	1		T13	3		T14	4
valid_sources[0x3c]	10613	1			T2	1		T4	3		T13	3
valid_sources[0x3d]	10575	1			T2	4		T4	1		T13	9
valid_sources[0x3e]	15630	1			T2	1		T12	4		T13	8
valid_sources[0x3f]	12478	1			T2	1		T12	12		T13	8
valid_sources[0x40]	11869	1			T2	1		T3	8		T13	2
valid_sources[0x41]	11502	1			T2	4		T4	3		T12	2
valid_sources[0x42]	12093	1			T2	1		T3	23		T13	3
valid_sources[0x43]	10857	1			T2	3		T3	4		T13	3
valid_sources[0x44]	26190	1			T2	2		T3	11		T4	3
valid_sources[0x45]	11168	1			T2	3		T4	1		T12	7
valid_sources[0x46]	12131	1			T2	1		T3	3		T4	1
valid_sources[0x47]	11638	1			T2	3		T3	7		T12	9
valid_sources[0x48]	15518	1			T2	3		T4	2		T13	8
valid_sources[0x49]	11795	1			T2	1		T4	2		T13	6
valid_sources[0x4a]	11101	1			T2	1		T3	1		T4	1
valid_sources[0x4b]	12038	1			T2	2		T3	15		T4	2
valid_sources[0x4c]	14074	1			T2	4		T3	3		T13	5
valid_sources[0x4d]	11238	1			T3	3		T4	6		T12	2
valid_sources[0x4e]	23693	1			T2	3		T4	3		T13	3
valid_sources[0x4f]	12406	1			T2	1		T3	4		T4	1
valid_sources[0x50]	10639	1			T2	3		T3	6		T4	2
valid_sources[0x51]	14780	1			T2	4		T4	1		T12	21
valid_sources[0x52]	11131	1			T2	1		T3	1		T4	1
valid_sources[0x53]	12873	1			T2	2		T3	11		T12	7
valid_sources[0x54]	10381	1			T3	7		T4	2		T13	1
valid_sources[0x55]	10302	1			T2	4		T3	3		T12	8
valid_sources[0x56]	11102	1			T2	3		T3	3		T12	2
valid_sources[0x57]	11168	1			T3	10		T13	4		T14	4
valid_sources[0x58]	11361	1			T2	1		T3	5		T12	8
valid_sources[0x59]	11224	1			T2	1		T13	4		T14	7
valid_sources[0x5a]	13041	1			T2	2		T12	5		T13	2
valid_sources[0x5b]	11791	1			T2	3		T3	2		T12	19
valid_sources[0x5c]	13127	1			T2	2		T3	2		T12	2
valid_sources[0x5d]	34252	1			T2	2		T12	3		T13	10
valid_sources[0x5e]	16992	1			T2	4		T13	2		T14	2
valid_sources[0x5f]	11061	1			T2	1		T3	2		T13	3
valid_sources[0x60]	10575	1			T2	1		T3	5		T13	3
valid_sources[0x61]	10697	1			T2	2		T13	5		T14	3
valid_sources[0x62]	14752	1			T3	5		T13	6		T14	8
valid_sources[0x63]	19575	1			T4	4		T13	4		T14	4
valid_sources[0x64]	11969	1			T2	2		T3	2		T4	1
valid_sources[0x65]	15371	1			T2	3		T3	6		T4	3
valid_sources[0x66]	10799	1			T2	1		T3	1		T12	2
valid_sources[0x67]	12379	1			T4	1		T12	19		T13	2
valid_sources[0x68]	12565	1			T4	1		T12	10		T13	3
valid_sources[0x69]	11169	1			T2	3		T3	3		T13	2
valid_sources[0x6a]	13080	1			T2	3		T3	1		T13	7
valid_sources[0x6b]	15354	1			T2	4		T3	1		T13	4
valid_sources[0x6c]	10870	1			T2	1		T12	15		T13	1
valid_sources[0x6d]	12048	1			T2	1		T13	1		T14	1
valid_sources[0x6e]	11429	1			T2	3		T3	6		T12	19
valid_sources[0x6f]	11358	1			T3	4		T13	6		T16	5
valid_sources[0x70]	27764	1			T4	3		T13	4		T14	1
valid_sources[0x71]	12118	1			T2	1		T3	9		T4	3
valid_sources[0x72]	11799	1			T2	2		T3	6		T4	2
valid_sources[0x73]	12966	1			T3	8		T13	3		T14	4
valid_sources[0x74]	20884	1			T2	1		T13	3		T14	2
valid_sources[0x75]	11745	1			T2	2		T4	2		T13	7
valid_sources[0x76]	11113	1			T2	1		T3	14		T4	1
valid_sources[0x77]	12636	1			T2	4		T3	3		T4	2
valid_sources[0x78]	11767	1			T2	2		T3	1		T4	1
valid_sources[0x79]	10778	1			T2	2		T4	1		T13	5
valid_sources[0x7a]	12340	1			T2	2		T3	4		T13	5
valid_sources[0x7b]	11913	1			T2	2		T13	6		T14	8
valid_sources[0x7c]	11068	1			T2	1		T4	1		T12	5
valid_sources[0x7d]	10436	1			T4	2		T13	7		T16	5
valid_sources[0x7e]	11282	1			T2	2		T3	13		T4	1
valid_sources[0x7f]	14544	1			T2	2		T4	2		T12	1
valid_sources[0x80]	11136	1			T2	2		T4	1		T13	13

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

316511

1

T1

112

T2

116

T3

158

values[0x0]

all_enables

biggest_size

144792

1

T1

104

T2

49

T3

73

values[0x1]

all_enables

biggest_size

131097

1

T1

110

T2

36

T3

56