Unified Coverage Report :: Module :: prim_secded_inv_72_64_dec

Module : prim_secded_inv_72_64_dec

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.32			99.32

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_72_64_dec.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[2].u_dec	93.15			93.15
tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[2].u_dec	93.15			93.15
tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[3].u_dec	93.15			93.15
tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[1].u_dec	93.15			93.15
tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[0].u_dec	93.15			93.15
tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[2].u_dec	93.15			93.15
tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[0].u_dec	95.89			95.89
tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[3].u_dec	95.89			95.89
tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[0].u_dec	95.89			95.89
tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[1].u_dec	95.89			95.89
tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[2].u_dec	95.89			95.89
tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[3].u_dec	97.26			97.26
tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[1].u_dec	97.26			97.26
tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[3].u_dec	97.26			97.26
tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[0].u_dec	97.95			97.95
tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[1].u_dec	98.63			98.63

---

Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[2].u_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.80	100.00	98.11		100.00	100.00	90.91	u_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[2].u_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.80	100.00	98.11		100.00	100.00	90.91	u_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[3].u_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.80	100.00	98.11		100.00	100.00	90.91	u_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[1].u_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.80	100.00	98.11		100.00	100.00	90.91	u_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[0].u_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.80	100.00	98.11		100.00	100.00	90.91	u_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[2].u_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.80	100.00	98.11		100.00	100.00	90.91	u_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[0].u_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89			95.89

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89			95.89

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.80	100.00	98.11		100.00	100.00	90.91	u_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[3].u_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89			95.89

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89			95.89

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.80	100.00	98.11		100.00	100.00	90.91	u_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[0].u_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89			95.89

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89			95.89

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.80	100.00	98.11		100.00	100.00	90.91	u_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[1].u_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89			95.89

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89			95.89

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.80	100.00	98.11		100.00	100.00	90.91	u_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[2].u_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89			95.89

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89			95.89

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.80	100.00	98.11		100.00	100.00	90.91	u_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[3].u_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.26			97.26

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.26			97.26

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.80	100.00	98.11		100.00	100.00	90.91	u_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[1].u_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.26			97.26

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.26			97.26

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.80	100.00	98.11		100.00	100.00	90.91	u_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[3].u_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.26			97.26

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.26			97.26

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.80	100.00	98.11		100.00	100.00	90.91	u_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[0].u_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.95			97.95

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.95			97.95

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.80	100.00	98.11		100.00	100.00	90.91	u_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[1].u_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.63			98.63

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.63			98.63

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.80	100.00	98.11		100.00	100.00	90.91	u_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	292	290	99.32
Total Bits 0->1	146	145	99.32
Total Bits 1->0	146	145	99.32

Ports	4	3	75.00
Port Bits	292	290	99.32
Port Bits 0->1	146	145	99.32
Port Bits 1->0	146	145	99.32

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	Yes	Yes	T141,T142,T143	Yes	T141,T142,T143	OUTPUT
err_o[0]	Yes	Yes	*T64,*T141,*T142	Yes	T64,T141,T142	OUTPUT
err_o[1]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[2].u_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[2].u_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[3].u_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[1].u_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[0].u_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T3,T12	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T3,T12	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[2].u_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[0].u_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	280	95.89
Total Bits 0->1	146	140	95.89
Total Bits 1->0	146	140	95.89

Ports	4	2	50.00
Port Bits	292	280	95.89
Port Bits 0->1	146	140	95.89
Port Bits 1->0	146	140	95.89

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T3,T4,T12	Yes	T2,T3,T4	INPUT
data_o[63:0]	Yes	Yes	T3,T4,T12	Yes	T2,T3,T4	OUTPUT
syndrome_o[0]	No	No		No		OUTPUT
syndrome_o[1]	Yes	Yes	*T144	Yes	T144	OUTPUT
syndrome_o[2]	No	No		No		OUTPUT
syndrome_o[3]	Yes	Yes	*T144	Yes	T144	OUTPUT
syndrome_o[5:4]	No	No		No		OUTPUT
syndrome_o[6]	Yes	Yes	*T144	Yes	T144	OUTPUT
syndrome_o[7]	No	No		No		OUTPUT
err_o[0]	Yes	Yes	*T144	Yes	T144	OUTPUT
err_o[1]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[3].u_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	280	95.89
Total Bits 0->1	146	140	95.89
Total Bits 1->0	146	140	95.89

Ports	4	2	50.00
Port Bits	292	280	95.89
Port Bits 0->1	146	140	95.89
Port Bits 1->0	146	140	95.89

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
syndrome_o[0]	Yes	Yes	*T142	Yes	T142	OUTPUT
syndrome_o[1]	No	No		No		OUTPUT
syndrome_o[2]	Yes	Yes	*T142	Yes	T142	OUTPUT
syndrome_o[4:3]	No	No		No		OUTPUT
syndrome_o[5]	Yes	Yes	*T142	Yes	T142	OUTPUT
syndrome_o[7:6]	No	No		No		OUTPUT
err_o[0]	Yes	Yes	*T142	Yes	T142	OUTPUT
err_o[1]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[0].u_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	280	95.89
Total Bits 0->1	146	140	95.89
Total Bits 1->0	146	140	95.89

Ports	4	2	50.00
Port Bits	292	280	95.89
Port Bits 0->1	146	140	95.89
Port Bits 1->0	146	140	95.89

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[2:0]	No	No		No		OUTPUT
syndrome_o[3]	Yes	Yes	*T145	Yes	T145	OUTPUT
syndrome_o[4]	No	No		No		OUTPUT
syndrome_o[5]	Yes	Yes	*T145	Yes	T145	OUTPUT
syndrome_o[6]	No	No		No		OUTPUT
syndrome_o[7]	Yes	Yes	T145	Yes	T145	OUTPUT
err_o[0]	Yes	Yes	*T145	Yes	T145	OUTPUT
err_o[1]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[1].gen_ecc_loop_words[1].u_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	280	95.89
Total Bits 0->1	146	140	95.89
Total Bits 1->0	146	140	95.89

Ports	4	2	50.00
Port Bits	292	280	95.89
Port Bits 0->1	146	140	95.89
Port Bits 1->0	146	140	95.89

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[0]	No	No		No		OUTPUT
syndrome_o[3:1]	Yes	Yes	T146	Yes	T146	OUTPUT
syndrome_o[7:4]	No	No		No		OUTPUT
err_o[0]	Yes	Yes	*T146	Yes	T146	OUTPUT
err_o[1]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[2].u_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	280	95.89
Total Bits 0->1	146	140	95.89
Total Bits 1->0	146	140	95.89

Ports	4	2	50.00
Port Bits	292	280	95.89
Port Bits 0->1	146	140	95.89
Port Bits 1->0	146	140	95.89

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
data_o[63:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
syndrome_o[3:0]	No	No		No		OUTPUT
syndrome_o[4]	Yes	Yes	*T146	Yes	T146	OUTPUT
syndrome_o[5]	No	No		No		OUTPUT
syndrome_o[7:6]	Yes	Yes	T146	Yes	T146	OUTPUT
err_o[0]	Yes	Yes	*T146	Yes	T146	OUTPUT
err_o[1]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[3].u_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	284	97.26
Total Bits 0->1	146	142	97.26
Total Bits 1->0	146	142	97.26

Ports	4	2	50.00
Port Bits	292	284	97.26
Port Bits 0->1	146	142	97.26
Port Bits 1->0	146	142	97.26

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T3,T4,T12	Yes	T2,T3,T4	INPUT
data_o[63:0]	Yes	Yes	T3,T4,T12	Yes	T2,T3,T4	OUTPUT
syndrome_o[0]	Yes	Yes	*T143	Yes	T143	OUTPUT
syndrome_o[1]	No	No		No		OUTPUT
syndrome_o[3:2]	Yes	Yes	T143	Yes	T143	OUTPUT
syndrome_o[4]	No	No		No		OUTPUT
syndrome_o[6:5]	Yes	Yes	T143	Yes	T143	OUTPUT
syndrome_o[7]	No	No		No		OUTPUT
err_o[0]	Yes	Yes	*T143	Yes	T143	OUTPUT
err_o[1]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[1].u_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	284	97.26
Total Bits 0->1	146	142	97.26
Total Bits 1->0	146	142	97.26

Ports	4	2	50.00
Port Bits	292	284	97.26
Port Bits 0->1	146	142	97.26
Port Bits 1->0	146	142	97.26

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[0]	No	No		No		OUTPUT
syndrome_o[2:1]	Yes	Yes	T147,*T145	Yes	T147,T145	OUTPUT
syndrome_o[4:3]	No	No		No		OUTPUT
syndrome_o[7:5]	Yes	Yes	T145,T147	Yes	T145,T147	OUTPUT
err_o[0]	Yes	Yes	*T147,*T145	Yes	T147,T145	OUTPUT
err_o[1]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[1].gen_ecc_loop_words[3].u_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	284	97.26
Total Bits 0->1	146	142	97.26
Total Bits 1->0	146	142	97.26

Ports	4	2	50.00
Port Bits	292	284	97.26
Port Bits 0->1	146	142	97.26
Port Bits 1->0	146	142	97.26

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[1:0]	Yes	Yes	T143	Yes	T143	OUTPUT
syndrome_o[3:2]	No	No		No		OUTPUT
syndrome_o[5:4]	Yes	Yes	T143	Yes	T143	OUTPUT
syndrome_o[6]	No	No		No		OUTPUT
syndrome_o[7]	Yes	Yes	T143	Yes	T143	OUTPUT
err_o[0]	Yes	Yes	*T143	Yes	T143	OUTPUT
err_o[1]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[1].gen_ecc_loop_shares[0].gen_ecc_loop_words[0].u_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	286	97.95
Total Bits 0->1	146	143	97.95
Total Bits 1->0	146	143	97.95

Ports	4	2	50.00
Port Bits	292	286	97.95
Port Bits 0->1	146	143	97.95
Port Bits 1->0	146	143	97.95

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
data_o[63:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
syndrome_o[0]	No	No		No		OUTPUT
syndrome_o[1]	Yes	Yes	*T147	Yes	T147	OUTPUT
syndrome_o[2]	No	No		No		OUTPUT
syndrome_o[7:3]	Yes	Yes	T147,T148	Yes	T147,T148	OUTPUT
err_o[0]	Yes	Yes	*T148,*T147	Yes	T148,T147	OUTPUT
err_o[1]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_ctrl.gen_ecc_loop_cdi[0].gen_ecc_loop_shares[0].gen_ecc_loop_words[1].u_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	288	98.63
Total Bits 0->1	146	144	98.63
Total Bits 1->0	146	144	98.63

Ports	4	2	50.00
Port Bits	292	288	98.63
Port Bits 0->1	146	144	98.63
Port Bits 1->0	146	144	98.63

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T3,T4,T12	Yes	T2,T3,T4	INPUT
data_o[63:0]	Yes	Yes	T3,T4,T12	Yes	T2,T3,T4	OUTPUT
syndrome_o[4:0]	Yes	Yes	*T141,*T64	Yes	T141,T64	OUTPUT
syndrome_o[5]	No	No		No		OUTPUT
syndrome_o[7:6]	Yes	Yes	T64	Yes	T64	OUTPUT
err_o[0]	Yes	Yes	*T64,*T141	Yes	T64,T141	OUTPUT
err_o[1]	No	No		No		OUTPUT

*Tests covering at least one bit in the range