Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	22684491	17161	0	0
attest_sw_binding_0_rd_A	22684491	3592	0	0
attest_sw_binding_1_rd_A	22684491	3693	0	0
attest_sw_binding_2_rd_A	22684491	3656	0	0
attest_sw_binding_3_rd_A	22684491	3580	0	0
attest_sw_binding_4_rd_A	22684491	3438	0	0
attest_sw_binding_5_rd_A	22684491	3502	0	0
attest_sw_binding_6_rd_A	22684491	3489	0	0
attest_sw_binding_7_rd_A	22684491	3566	0	0
intr_enable_rd_A	22684491	3898	0	0
key_version_rd_A	22684491	3603	0	0
max_creator_key_ver_regwen_rd_A	22684491	3576	0	0
max_owner_int_key_ver_regwen_rd_A	22684491	3711	0	0
max_owner_key_ver_regwen_rd_A	22684491	3515	0	0
reseed_interval_regwen_rd_A	22684491	3576	0	0
salt_0_rd_A	22684491	3506	0	0
salt_1_rd_A	22684491	3568	0	0
salt_2_rd_A	22684491	3576	0	0
salt_3_rd_A	22684491	3548	0	0
salt_4_rd_A	22684491	3549	0	0
salt_5_rd_A	22684491	3322	0	0
salt_6_rd_A	22684491	3552	0	0
salt_7_rd_A	22684491	3648	0	0
sealing_sw_binding_0_rd_A	22684491	3615	0	0
sealing_sw_binding_1_rd_A	22684491	3693	0	0
sealing_sw_binding_2_rd_A	22684491	3544	0	0
sealing_sw_binding_3_rd_A	22684491	3587	0	0
sealing_sw_binding_4_rd_A	22684491	3586	0	0
sealing_sw_binding_5_rd_A	22684491	3440	0	0
sealing_sw_binding_6_rd_A	22684491	3713	0	0
sealing_sw_binding_7_rd_A	22684491	3605	0	0
sideload_clear_rd_A	22684491	3543	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22684491	17161	0	0
T24	182448	0	0	0
T39	1807	0	0	0
T40	8572	0	0	0
T50	61960	219	0	0
T56	7406	0	0	0
T57	3763	0	0	0
T67	0	903	0	0
T69	0	25	0	0
T70	2052	0	0	0
T72	0	968	0	0
T76	4286	0	0	0
T77	5378	0	0	0
T78	4834	0	0	0
T105	0	1777	0	0
T117	0	231	0	0
T118	0	414	0	0
T119	0	297	0	0
T120	0	149	0	0
T121	0	182	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22684491	3592	0	0
T24	182448	0	0	0
T39	1807	0	0	0
T40	8572	0	0	0
T50	61960	31	0	0
T56	7406	0	0	0
T57	3763	0	0	0
T70	2052	0	0	0
T76	4286	0	0	0
T77	5378	0	0	0
T78	4834	0	0	0
T120	0	52	0	0
T137	0	6	0	0
T151	0	31	0	0
T152	0	57	0	0
T179	0	22	0	0
T180	0	13	0	0
T181	0	4	0	0
T182	0	16	0	0
T183	0	10	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22684491	3693	0	0
T24	182448	0	0	0
T39	1807	0	0	0
T40	8572	0	0	0
T50	61960	59	0	0
T56	7406	0	0	0
T57	3763	0	0	0
T70	2052	0	0	0
T76	4286	0	0	0
T77	5378	0	0	0
T78	4834	0	0	0
T120	0	34	0	0
T151	0	25	0	0
T152	0	73	0	0
T179	0	39	0	0
T180	0	4	0	0
T181	0	7	0	0
T182	0	9	0	0
T183	0	6	0	0
T184	0	8	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22684491	3656	0	0
T24	182448	0	0	0
T39	1807	0	0	0
T40	8572	0	0	0
T50	61960	16	0	0
T56	7406	0	0	0
T57	3763	0	0	0
T70	2052	0	0	0
T76	4286	0	0	0
T77	5378	0	0	0
T78	4834	0	0	0
T120	0	40	0	0
T137	0	5	0	0
T151	0	22	0	0
T152	0	83	0	0
T179	0	18	0	0
T181	0	5	0	0
T182	0	3	0	0
T183	0	7	0	0
T184	0	9	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22684491	3580	0	0
T24	182448	0	0	0
T39	1807	0	0	0
T40	8572	0	0	0
T50	61960	32	0	0
T56	7406	0	0	0
T57	3763	0	0	0
T70	2052	0	0	0
T76	4286	0	0	0
T77	5378	0	0	0
T78	4834	0	0	0
T120	0	25	0	0
T137	0	8	0	0
T151	0	30	0	0
T152	0	68	0	0
T179	0	29	0	0
T180	0	12	0	0
T181	0	14	0	0
T182	0	7	0	0
T183	0	16	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22684491	3438	0	0
T24	182448	0	0	0
T39	1807	0	0	0
T40	8572	0	0	0
T50	61960	27	0	0
T56	7406	0	0	0
T57	3763	0	0	0
T70	2052	0	0	0
T76	4286	0	0	0
T77	5378	0	0	0
T78	4834	0	0	0
T120	0	38	0	0
T151	0	20	0	0
T152	0	75	0	0
T179	0	39	0	0
T180	0	3	0	0
T181	0	4	0	0
T182	0	1	0	0
T183	0	12	0	0
T184	0	4	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22684491	3502	0	0
T24	182448	0	0	0
T39	1807	0	0	0
T40	8572	0	0	0
T50	61960	38	0	0
T56	7406	0	0	0
T57	3763	0	0	0
T70	2052	0	0	0
T76	4286	0	0	0
T77	5378	0	0	0
T78	4834	0	0	0
T120	0	19	0	0
T137	0	4	0	0
T151	0	18	0	0
T152	0	83	0	0
T179	0	22	0	0
T180	0	22	0	0
T181	0	7	0	0
T182	0	4	0	0
T183	0	3	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22684491	3489	0	0
T24	182448	0	0	0
T39	1807	0	0	0
T40	8572	0	0	0
T50	61960	38	0	0
T56	7406	0	0	0
T57	3763	0	0	0
T70	2052	0	0	0
T76	4286	0	0	0
T77	5378	0	0	0
T78	4834	0	0	0
T120	0	29	0	0
T137	0	5	0	0
T138	0	28	0	0
T151	0	21	0	0
T152	0	90	0	0
T179	0	38	0	0
T181	0	13	0	0
T182	0	8	0	0
T183	0	10	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22684491	3566	0	0
T24	182448	0	0	0
T39	1807	0	0	0
T40	8572	0	0	0
T50	61960	32	0	0
T56	7406	0	0	0
T57	3763	0	0	0
T70	2052	0	0	0
T76	4286	0	0	0
T77	5378	0	0	0
T78	4834	0	0	0
T120	0	14	0	0
T151	0	30	0	0
T152	0	93	0	0
T179	0	23	0	0
T180	0	3	0	0
T181	0	12	0	0
T182	0	10	0	0
T183	0	15	0	0
T184	0	6	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22684491	3898	0	0
T5	0	29	0	0
T6	0	11	0	0
T24	182448	0	0	0
T39	1807	0	0	0
T40	8572	0	0	0
T50	61960	54	0	0
T56	7406	0	0	0
T57	3763	0	0	0
T70	2052	0	0	0
T76	4286	0	0	0
T77	5378	0	0	0
T78	4834	0	0	0
T120	0	32	0	0
T179	0	54	0	0
T185	0	26	0	0
T186	0	87	0	0
T187	0	8	0	0
T188	0	2	0	0
T189	0	11	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22684491	3603	0	0
T24	182448	0	0	0
T39	1807	0	0	0
T40	8572	0	0	0
T50	61960	16	0	0
T56	7406	0	0	0
T57	3763	0	0	0
T70	2052	0	0	0
T76	4286	0	0	0
T77	5378	0	0	0
T78	4834	0	0	0
T120	0	16	0	0
T151	0	13	0	0
T152	0	67	0	0
T179	0	43	0	0
T180	0	5	0	0
T181	0	7	0	0
T182	0	14	0	0
T183	0	13	0	0
T184	0	2	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22684491	3576	0	0
T24	182448	0	0	0
T39	1807	0	0	0
T40	8572	0	0	0
T50	61960	11	0	0
T56	7406	0	0	0
T57	3763	0	0	0
T70	2052	0	0	0
T76	4286	0	0	0
T77	5378	0	0	0
T78	4834	0	0	0
T120	0	39	0	0
T151	0	13	0	0
T152	0	74	0	0
T179	0	22	0	0
T180	0	22	0	0
T181	0	15	0	0
T182	0	16	0	0
T183	0	6	0	0
T184	0	6	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22684491	3711	0	0
T24	182448	0	0	0
T39	1807	0	0	0
T40	8572	0	0	0
T50	61960	39	0	0
T56	7406	0	0	0
T57	3763	0	0	0
T70	2052	0	0	0
T76	4286	0	0	0
T77	5378	0	0	0
T78	4834	0	0	0
T120	0	37	0	0
T137	0	6	0	0
T151	0	30	0	0
T152	0	75	0	0
T179	0	40	0	0
T181	0	6	0	0
T182	0	6	0	0
T183	0	15	0	0
T184	0	5	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22684491	3515	0	0
T24	182448	0	0	0
T39	1807	0	0	0
T40	8572	0	0	0
T50	61960	25	0	0
T56	7406	0	0	0
T57	3763	0	0	0
T70	2052	0	0	0
T76	4286	0	0	0
T77	5378	0	0	0
T78	4834	0	0	0
T120	0	51	0	0
T137	0	9	0	0
T151	0	24	0	0
T152	0	83	0	0
T179	0	22	0	0
T181	0	16	0	0
T182	0	2	0	0
T183	0	12	0	0
T184	0	12	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22684491	3576	0	0
T24	182448	0	0	0
T39	1807	0	0	0
T40	8572	0	0	0
T50	61960	35	0	0
T56	7406	0	0	0
T57	3763	0	0	0
T70	2052	0	0	0
T76	4286	0	0	0
T77	5378	0	0	0
T78	4834	0	0	0
T120	0	38	0	0
T137	0	11	0	0
T151	0	32	0	0
T152	0	62	0	0
T179	0	24	0	0
T181	0	8	0	0
T182	0	3	0	0
T183	0	3	0	0
T184	0	9	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22684491	3506	0	0
T24	182448	0	0	0
T39	1807	0	0	0
T40	8572	0	0	0
T50	61960	24	0	0
T56	7406	0	0	0
T57	3763	0	0	0
T70	2052	0	0	0
T76	4286	0	0	0
T77	5378	0	0	0
T78	4834	0	0	0
T120	0	28	0	0
T137	0	15	0	0
T151	0	14	0	0
T152	0	77	0	0
T179	0	19	0	0
T181	0	1	0	0
T182	0	8	0	0
T183	0	10	0	0
T184	0	4	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22684491	3568	0	0
T24	182448	0	0	0
T39	1807	0	0	0
T40	8572	0	0	0
T50	61960	19	0	0
T56	7406	0	0	0
T57	3763	0	0	0
T70	2052	0	0	0
T76	4286	0	0	0
T77	5378	0	0	0
T78	4834	0	0	0
T120	0	22	0	0
T137	0	16	0	0
T138	0	56	0	0
T151	0	7	0	0
T152	0	71	0	0
T179	0	39	0	0
T180	0	4	0	0
T181	0	1	0	0
T182	0	8	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22684491	3576	0	0
T24	182448	0	0	0
T39	1807	0	0	0
T40	8572	0	0	0
T50	61960	44	0	0
T56	7406	0	0	0
T57	3763	0	0	0
T70	2052	0	0	0
T76	4286	0	0	0
T77	5378	0	0	0
T78	4834	0	0	0
T120	0	35	0	0
T137	0	7	0	0
T151	0	28	0	0
T152	0	80	0	0
T179	0	19	0	0
T181	0	16	0	0
T182	0	8	0	0
T183	0	7	0	0
T184	0	7	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22684491	3548	0	0
T24	182448	0	0	0
T39	1807	0	0	0
T40	8572	0	0	0
T50	61960	15	0	0
T56	7406	0	0	0
T57	3763	0	0	0
T70	2052	0	0	0
T76	4286	0	0	0
T77	5378	0	0	0
T78	4834	0	0	0
T120	0	19	0	0
T137	0	9	0	0
T151	0	31	0	0
T152	0	51	0	0
T179	0	29	0	0
T180	0	9	0	0
T181	0	8	0	0
T182	0	6	0	0
T183	0	3	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22684491	3549	0	0
T24	182448	0	0	0
T39	1807	0	0	0
T40	8572	0	0	0
T50	61960	42	0	0
T56	7406	0	0	0
T57	3763	0	0	0
T70	2052	0	0	0
T76	4286	0	0	0
T77	5378	0	0	0
T78	4834	0	0	0
T120	0	25	0	0
T137	0	6	0	0
T151	0	46	0	0
T152	0	89	0	0
T179	0	28	0	0
T180	0	7	0	0
T181	0	21	0	0
T182	0	11	0	0
T183	0	14	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22684491	3322	0	0
T24	182448	0	0	0
T39	1807	0	0	0
T40	8572	0	0	0
T50	61960	24	0	0
T56	7406	0	0	0
T57	3763	0	0	0
T70	2052	0	0	0
T76	4286	0	0	0
T77	5378	0	0	0
T78	4834	0	0	0
T120	0	40	0	0
T137	0	13	0	0
T138	0	24	0	0
T151	0	14	0	0
T152	0	67	0	0
T179	0	25	0	0
T181	0	1	0	0
T182	0	2	0	0
T183	0	13	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22684491	3552	0	0
T24	182448	0	0	0
T39	1807	0	0	0
T40	8572	0	0	0
T50	61960	16	0	0
T56	7406	0	0	0
T57	3763	0	0	0
T70	2052	0	0	0
T76	4286	0	0	0
T77	5378	0	0	0
T78	4834	0	0	0
T120	0	33	0	0
T151	0	15	0	0
T152	0	73	0	0
T179	0	31	0	0
T180	0	7	0	0
T181	0	8	0	0
T182	0	3	0	0
T183	0	13	0	0
T190	0	1	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22684491	3648	0	0
T24	182448	0	0	0
T39	1807	0	0	0
T40	8572	0	0	0
T50	61960	33	0	0
T56	7406	0	0	0
T57	3763	0	0	0
T70	2052	0	0	0
T76	4286	0	0	0
T77	5378	0	0	0
T78	4834	0	0	0
T120	0	22	0	0
T151	0	23	0	0
T152	0	64	0	0
T179	0	38	0	0
T180	0	2	0	0
T181	0	13	0	0
T182	0	6	0	0
T183	0	10	0	0
T184	0	7	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22684491	3615	0	0
T24	182448	0	0	0
T39	1807	0	0	0
T40	8572	0	0	0
T50	61960	27	0	0
T56	7406	0	0	0
T57	3763	0	0	0
T70	2052	0	0	0
T76	4286	0	0	0
T77	5378	0	0	0
T78	4834	0	0	0
T120	0	32	0	0
T137	0	11	0	0
T151	0	29	0	0
T152	0	59	0	0
T179	0	30	0	0
T180	0	14	0	0
T181	0	6	0	0
T182	0	4	0	0
T183	0	13	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22684491	3693	0	0
T24	182448	0	0	0
T39	1807	0	0	0
T40	8572	0	0	0
T50	61960	27	0	0
T56	7406	0	0	0
T57	3763	0	0	0
T70	2052	0	0	0
T76	4286	0	0	0
T77	5378	0	0	0
T78	4834	0	0	0
T120	0	46	0	0
T137	0	6	0	0
T151	0	25	0	0
T152	0	104	0	0
T179	0	17	0	0
T180	0	10	0	0
T181	0	8	0	0
T182	0	11	0	0
T183	0	6	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22684491	3544	0	0
T24	182448	0	0	0
T39	1807	0	0	0
T40	8572	0	0	0
T50	61960	39	0	0
T56	7406	0	0	0
T57	3763	0	0	0
T70	2052	0	0	0
T76	4286	0	0	0
T77	5378	0	0	0
T78	4834	0	0	0
T120	0	24	0	0
T137	0	13	0	0
T138	0	29	0	0
T151	0	27	0	0
T152	0	78	0	0
T179	0	25	0	0
T181	0	9	0	0
T183	0	11	0	0
T191	0	446	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22684491	3587	0	0
T24	182448	0	0	0
T39	1807	0	0	0
T40	8572	0	0	0
T50	61960	13	0	0
T56	7406	0	0	0
T57	3763	0	0	0
T70	2052	0	0	0
T76	4286	0	0	0
T77	5378	0	0	0
T78	4834	0	0	0
T120	0	42	0	0
T151	0	31	0	0
T152	0	84	0	0
T179	0	33	0	0
T180	0	6	0	0
T181	0	5	0	0
T182	0	12	0	0
T183	0	15	0	0
T184	0	17	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22684491	3586	0	0
T24	182448	0	0	0
T39	1807	0	0	0
T40	8572	0	0	0
T50	61960	25	0	0
T56	7406	0	0	0
T57	3763	0	0	0
T70	2052	0	0	0
T76	4286	0	0	0
T77	5378	0	0	0
T78	4834	0	0	0
T120	0	36	0	0
T137	0	7	0	0
T151	0	14	0	0
T152	0	70	0	0
T179	0	27	0	0
T181	0	14	0	0
T182	0	4	0	0
T183	0	9	0	0
T184	0	9	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22684491	3440	0	0
T24	182448	0	0	0
T39	1807	0	0	0
T40	8572	0	0	0
T50	61960	12	0	0
T56	7406	0	0	0
T57	3763	0	0	0
T70	2052	0	0	0
T76	4286	0	0	0
T77	5378	0	0	0
T78	4834	0	0	0
T120	0	31	0	0
T151	0	19	0	0
T152	0	70	0	0
T179	0	10	0	0
T180	0	13	0	0
T181	0	6	0	0
T182	0	10	0	0
T183	0	2	0	0
T184	0	9	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22684491	3713	0	0
T24	182448	0	0	0
T39	1807	0	0	0
T40	8572	0	0	0
T50	61960	30	0	0
T56	7406	0	0	0
T57	3763	0	0	0
T70	2052	0	0	0
T76	4286	0	0	0
T77	5378	0	0	0
T78	4834	0	0	0
T120	0	34	0	0
T151	0	9	0	0
T152	0	83	0	0
T179	0	28	0	0
T180	0	4	0	0
T181	0	10	0	0
T182	0	6	0	0
T183	0	14	0	0
T184	0	1	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22684491	3605	0	0
T24	182448	0	0	0
T39	1807	0	0	0
T40	8572	0	0	0
T50	61960	70	0	0
T56	7406	0	0	0
T57	3763	0	0	0
T70	2052	0	0	0
T76	4286	0	0	0
T77	5378	0	0	0
T78	4834	0	0	0
T120	0	36	0	0
T137	0	7	0	0
T151	0	29	0	0
T152	0	73	0	0
T179	0	42	0	0
T181	0	15	0	0
T182	0	5	0	0
T183	0	2	0	0
T184	0	5	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22684491	3543	0	0
T24	182448	0	0	0
T39	1807	0	0	0
T40	8572	0	0	0
T50	61960	32	0	0
T56	7406	0	0	0
T57	3763	0	0	0
T70	2052	0	0	0
T76	4286	0	0	0
T77	5378	0	0	0
T78	4834	0	0	0
T120	0	27	0	0
T137	0	10	0	0
T151	0	10	0	0
T152	0	90	0	0
T179	0	25	0	0
T181	0	4	0	0
T182	0	8	0	0
T183	0	2	0	0
T184	0	6	0	0