Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3578743	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

658839

1

T1

623

T2

252

T3

339

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3800359	1			T1	5929		T2	2073		T3	498
values[0x0]	217021	1			T1	219		T2	59		T3	115
values[0x1]	220202	1			T1	206		T2	59		T3	139

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2449392	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1788190

1

T1

2524

T2

827

T3

426

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12003	1			T1	19		T2	6		T14	4
valid_sources[0x01]	14878	1			T1	31		T2	15		T3	6
valid_sources[0x02]	49676	1			T1	34		T2	7		T13	35
valid_sources[0x03]	12259	1			T1	23		T2	11		T3	5
valid_sources[0x04]	11699	1			T1	34		T2	7		T13	21
valid_sources[0x05]	12558	1			T1	21		T2	11		T13	1
valid_sources[0x06]	11734	1			T1	31		T2	6		T13	2
valid_sources[0x07]	12660	1			T1	27		T2	9		T3	15
valid_sources[0x08]	16786	1			T1	19		T2	6		T14	9
valid_sources[0x09]	12131	1			T1	17		T2	7		T3	9
valid_sources[0x0a]	12419	1			T1	22		T2	9		T13	4
valid_sources[0x0b]	12966	1			T1	8		T2	12		T3	14
valid_sources[0x0c]	14661	1			T1	12		T2	6		T13	4
valid_sources[0x0d]	12783	1			T1	22		T2	9		T14	13
valid_sources[0x0e]	11428	1			T1	36		T2	6		T3	9
valid_sources[0x0f]	14964	1			T1	24		T2	11		T12	1
valid_sources[0x10]	11853	1			T1	23		T2	10		T13	5
valid_sources[0x11]	11780	1			T1	23		T2	13		T13	1
valid_sources[0x12]	12183	1			T1	20		T2	6		T14	4
valid_sources[0x13]	11916	1			T1	34		T2	8		T13	9
valid_sources[0x14]	11270	1			T1	24		T2	3		T14	2
valid_sources[0x15]	12338	1			T1	18		T2	12		T3	12
valid_sources[0x16]	12889	1			T1	10		T2	4		T3	17
valid_sources[0x17]	39750	1			T1	16		T2	9		T14	6
valid_sources[0x18]	18083	1			T1	17		T2	12		T3	28
valid_sources[0x19]	13534	1			T1	21		T2	6		T3	3
valid_sources[0x1a]	16245	1			T1	38		T2	7		T3	11
valid_sources[0x1b]	11426	1			T1	25		T2	9		T13	26
valid_sources[0x1c]	18196	1			T1	23		T2	7		T83	6
valid_sources[0x1d]	21778	1			T1	16		T2	6		T13	9
valid_sources[0x1e]	32292	1			T1	25		T2	7		T13	3
valid_sources[0x1f]	14833	1			T1	15		T2	5		T12	1
valid_sources[0x20]	12862	1			T1	14		T2	11		T13	1
valid_sources[0x21]	13244	1			T1	26		T2	10		T32	5
valid_sources[0x22]	12278	1			T1	32		T2	9		T3	2
valid_sources[0x23]	11208	1			T1	15		T2	9		T13	12
valid_sources[0x24]	11125	1			T1	24		T2	8		T13	10
valid_sources[0x25]	12662	1			T1	20		T2	7		T13	13
valid_sources[0x26]	11708	1			T1	21		T2	6		T14	4
valid_sources[0x27]	13375	1			T1	19		T2	6		T14	6
valid_sources[0x28]	11157	1			T1	19		T2	7		T13	7
valid_sources[0x29]	18679	1			T1	27		T2	8		T3	1
valid_sources[0x2a]	12571	1			T1	35		T2	6		T13	5
valid_sources[0x2b]	13432	1			T1	24		T2	11		T13	7
valid_sources[0x2c]	11555	1			T1	26		T2	4		T3	30
valid_sources[0x2d]	13879	1			T1	33		T2	9		T32	13
valid_sources[0x2e]	18354	1			T1	17		T2	8		T14	3
valid_sources[0x2f]	12571	1			T1	34		T2	9		T3	3
valid_sources[0x30]	11228	1			T1	26		T2	9		T14	51
valid_sources[0x31]	11165	1			T1	15		T2	5		T14	4
valid_sources[0x32]	36647	1			T1	54		T2	7		T13	7
valid_sources[0x33]	11394	1			T1	33		T2	8		T13	8
valid_sources[0x34]	13913	1			T1	28		T2	8		T13	5
valid_sources[0x35]	11341	1			T1	12		T2	7		T13	1
valid_sources[0x36]	12457	1			T1	22		T2	8		T14	5
valid_sources[0x37]	12009	1			T1	24		T2	8		T13	4
valid_sources[0x38]	14992	1			T1	32		T2	8		T3	13
valid_sources[0x39]	11885	1			T1	30		T2	8		T13	1
valid_sources[0x3a]	13271	1			T1	26		T2	4		T14	6
valid_sources[0x3b]	11438	1			T1	27		T2	10		T15	88
valid_sources[0x3c]	11742	1			T1	28		T2	4		T13	5
valid_sources[0x3d]	11318	1			T1	12		T2	11		T13	3
valid_sources[0x3e]	64161	1			T1	22		T2	11		T13	5
valid_sources[0x3f]	34150	1			T1	16		T2	8		T3	23
valid_sources[0x40]	13873	1			T1	26		T2	10		T13	2
valid_sources[0x41]	12630	1			T1	28		T2	4		T3	25
valid_sources[0x42]	12084	1			T1	30		T2	10		T13	27
valid_sources[0x43]	11489	1			T1	25		T2	6		T14	2
valid_sources[0x44]	12366	1			T1	24		T2	7		T3	3
valid_sources[0x45]	10946	1			T1	21		T2	7		T3	9
valid_sources[0x46]	20520	1			T1	21		T2	8		T3	13
valid_sources[0x47]	12590	1			T1	31		T2	10		T3	11
valid_sources[0x48]	11712	1			T1	27		T2	11		T13	11
valid_sources[0x49]	12931	1			T1	27		T2	12		T32	1
valid_sources[0x4a]	14397	1			T1	33		T2	8		T13	2
valid_sources[0x4b]	13487	1			T1	27		T2	8		T3	9
valid_sources[0x4c]	11929	1			T1	34		T2	12		T13	23
valid_sources[0x4d]	11510	1			T1	23		T2	13		T13	10
valid_sources[0x4e]	13206	1			T1	18		T2	15		T13	8
valid_sources[0x4f]	13810	1			T1	28		T2	8		T13	1
valid_sources[0x50]	12699	1			T1	33		T2	7		T13	1
valid_sources[0x51]	11859	1			T1	10		T2	10		T13	12
valid_sources[0x52]	11343	1			T1	37		T2	5		T3	13
valid_sources[0x53]	12672	1			T1	38		T2	9		T3	29
valid_sources[0x54]	73375	1			T1	9		T2	7		T3	22
valid_sources[0x55]	11510	1			T1	24		T2	6		T13	7
valid_sources[0x56]	260535	1			T1	19		T2	17		T13	4
valid_sources[0x57]	12769	1			T1	26		T2	7		T3	6
valid_sources[0x58]	11221	1			T1	18		T2	11		T3	13
valid_sources[0x59]	11879	1			T1	28		T2	6		T13	28
valid_sources[0x5a]	11798	1			T1	20		T2	6		T13	2
valid_sources[0x5b]	51511	1			T1	15		T2	11		T13	6
valid_sources[0x5c]	12184	1			T1	33		T2	10		T14	3
valid_sources[0x5d]	12216	1			T1	20		T2	13		T12	1
valid_sources[0x5e]	23260	1			T1	13		T2	7		T32	1
valid_sources[0x5f]	12946	1			T1	24		T2	15		T12	1
valid_sources[0x60]	11363	1			T1	37		T2	7		T14	2
valid_sources[0x61]	16771	1			T1	29		T2	5		T13	1
valid_sources[0x62]	14017	1			T1	16		T2	9		T3	11
valid_sources[0x63]	11703	1			T1	28		T2	3		T13	15
valid_sources[0x64]	12612	1			T1	33		T2	5		T13	1
valid_sources[0x65]	18478	1			T1	33		T2	12		T13	1
valid_sources[0x66]	11220	1			T1	33		T2	13		T14	8
valid_sources[0x67]	24689	1			T1	24		T2	7		T3	26
valid_sources[0x68]	13188	1			T1	30		T2	10		T3	11
valid_sources[0x69]	13543	1			T1	13		T2	4		T13	20
valid_sources[0x6a]	11819	1			T1	21		T2	11		T13	2
valid_sources[0x6b]	11423	1			T1	27		T2	9		T3	1
valid_sources[0x6c]	12802	1			T1	27		T2	11		T14	5
valid_sources[0x6d]	14960	1			T1	23		T2	8		T14	6
valid_sources[0x6e]	12433	1			T1	28		T2	9		T13	13
valid_sources[0x6f]	10982	1			T1	27		T2	4		T3	2
valid_sources[0x70]	11816	1			T1	24		T2	8		T3	10
valid_sources[0x71]	11965	1			T1	26		T2	7		T13	17
valid_sources[0x72]	12445	1			T1	25		T2	8		T14	7
valid_sources[0x73]	12439	1			T1	17		T2	10		T32	8
valid_sources[0x74]	12218	1			T1	14		T2	13		T13	9
valid_sources[0x75]	12527	1			T1	42		T2	11		T14	1
valid_sources[0x76]	11746	1			T1	25		T2	6		T15	8
valid_sources[0x77]	12412	1			T1	21		T2	9		T3	21
valid_sources[0x78]	12213	1			T1	18		T2	5		T14	7
valid_sources[0x79]	12447	1			T1	24		T2	11		T13	15
valid_sources[0x7a]	11676	1			T1	31		T2	11		T13	10
valid_sources[0x7b]	13049	1			T1	23		T2	7		T3	13
valid_sources[0x7c]	12700	1			T1	7		T2	7		T3	19
valid_sources[0x7d]	10820	1			T1	29		T2	6		T3	18
valid_sources[0x7e]	12210	1			T1	17		T2	10		T12	1
valid_sources[0x7f]	11197	1			T1	23		T2	8		T13	9
valid_sources[0x80]	11571	1			T1	32		T2	12		T13	21

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

359905

1

T1

314

T2

211

T3

195

values[0x0]

all_enables

biggest_size

157069

1

T1

162

T2

23

T3

67

values[0x1]

all_enables

biggest_size

141865

1

T1

147

T2

18

T3

77