Unified Coverage Report :: Module :: prim_mubi4_sender

Module : prim_mubi4_sender

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_ctrl.u_hw_sel	100.00	100.00					100.00

---

Module Instance : tb.dut.u_ctrl.u_hw_sel

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.80	100.00	98.11		100.00	100.00	90.91	u_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Module : prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	27063094	26903142	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27063094	26903142	0	0
T1	15462	15385	0	0
T2	7530	7464	0	0
T3	3335	3276	0	0
T4	6275	6149	0	0
T11	962	911	0	0
T12	1032	974	0	0
T13	5101	5003	0	0
T14	16813	16722	0	0
T15	12415	12333	0	0
T16	4589	4508	0	0