Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3151979	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

632944

1

T1

9

T2

71

T3

2298

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3362105	1			T1	1		T2	264		T3	2967
values[0x0]	209500	1			T1	6		T2	43		T3	774
values[0x1]	213318	1			T1	13		T2	33		T3	788

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2162632	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1622291

1

T1

11

T2

153

T3

2792

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	41790	1			T3	19		T4	27		T5	16
valid_sources[0x01]	10611	1			T3	15		T4	27		T5	6
valid_sources[0x02]	10739	1			T3	23		T4	16		T5	13
valid_sources[0x03]	11437	1			T3	15		T4	30		T5	8
valid_sources[0x04]	11153	1			T3	11		T4	21		T5	9
valid_sources[0x05]	11915	1			T3	19		T4	11		T5	8
valid_sources[0x06]	11929	1			T3	27		T4	44		T5	11
valid_sources[0x07]	11494	1			T3	14		T4	51		T5	5
valid_sources[0x08]	11416	1			T3	24		T4	38		T5	8
valid_sources[0x09]	11255	1			T3	14		T4	35		T5	11
valid_sources[0x0a]	11539	1			T3	19		T4	27		T5	14
valid_sources[0x0b]	10749	1			T3	20		T4	17		T5	10
valid_sources[0x0c]	19835	1			T3	32		T4	26		T5	9
valid_sources[0x0d]	26714	1			T3	22		T4	22		T5	8
valid_sources[0x0e]	10865	1			T3	13		T4	31		T5	11
valid_sources[0x0f]	23660	1			T3	13		T4	30		T5	12
valid_sources[0x10]	10821	1			T3	18		T4	18		T5	11
valid_sources[0x11]	11853	1			T3	17		T4	58		T5	13
valid_sources[0x12]	12939	1			T3	26		T4	31		T5	10
valid_sources[0x13]	10941	1			T2	203		T3	16		T4	38
valid_sources[0x14]	12018	1			T2	63		T3	10		T4	22
valid_sources[0x15]	10767	1			T3	19		T4	36		T5	7
valid_sources[0x16]	14673	1			T3	11		T4	14		T5	3
valid_sources[0x17]	11574	1			T3	18		T4	30		T5	11
valid_sources[0x18]	11956	1			T3	19		T4	29		T5	8
valid_sources[0x19]	18055	1			T3	23		T4	17		T5	12
valid_sources[0x1a]	10888	1			T3	18		T4	19		T5	8
valid_sources[0x1b]	18995	1			T3	21		T4	14		T5	6
valid_sources[0x1c]	10397	1			T3	21		T4	21		T5	11
valid_sources[0x1d]	10384	1			T3	11		T4	23		T5	7
valid_sources[0x1e]	13255	1			T1	3		T3	16		T4	18
valid_sources[0x1f]	11844	1			T3	18		T4	19		T5	9
valid_sources[0x20]	10919	1			T3	20		T4	29		T5	7
valid_sources[0x21]	11009	1			T3	18		T4	38		T5	9
valid_sources[0x22]	11603	1			T3	14		T4	45		T5	7
valid_sources[0x23]	11231	1			T3	12		T4	35		T5	10
valid_sources[0x24]	11402	1			T3	14		T4	31		T5	9
valid_sources[0x25]	17291	1			T3	31		T4	27		T5	12
valid_sources[0x26]	12033	1			T3	16		T4	26		T5	8
valid_sources[0x27]	11677	1			T3	14		T4	39		T5	12
valid_sources[0x28]	11715	1			T3	8		T4	34		T5	13
valid_sources[0x29]	10720	1			T3	17		T4	23		T5	12
valid_sources[0x2a]	11276	1			T3	19		T4	29		T5	5
valid_sources[0x2b]	11180	1			T3	9		T4	35		T5	10
valid_sources[0x2c]	11546	1			T3	12		T4	27		T5	15
valid_sources[0x2d]	10519	1			T3	19		T4	22		T5	8
valid_sources[0x2e]	11321	1			T3	16		T4	34		T5	14
valid_sources[0x2f]	10514	1			T3	10		T4	24		T5	12
valid_sources[0x30]	10862	1			T3	25		T4	26		T5	8
valid_sources[0x31]	11683	1			T3	24		T4	13		T5	16
valid_sources[0x32]	12390	1			T3	19		T4	26		T5	13
valid_sources[0x33]	11247	1			T3	15		T4	23		T5	9
valid_sources[0x34]	10589	1			T3	14		T4	23		T5	8
valid_sources[0x35]	11074	1			T3	29		T4	32		T5	8
valid_sources[0x36]	12135	1			T3	13		T4	36		T5	16
valid_sources[0x37]	11244	1			T3	8		T4	32		T5	11
valid_sources[0x38]	10995	1			T3	18		T4	21		T5	10
valid_sources[0x39]	11679	1			T1	3		T3	20		T4	25
valid_sources[0x3a]	11952	1			T3	16		T4	21		T5	12
valid_sources[0x3b]	11713	1			T3	20		T4	14		T5	9
valid_sources[0x3c]	11128	1			T3	18		T4	19		T5	5
valid_sources[0x3d]	11676	1			T3	15		T4	44		T5	16
valid_sources[0x3e]	10904	1			T1	1		T3	38		T4	29
valid_sources[0x3f]	11333	1			T3	13		T4	61		T5	6
valid_sources[0x40]	462133	1			T3	18		T4	30		T5	6
valid_sources[0x41]	12522	1			T3	11		T4	21		T5	7
valid_sources[0x42]	10043	1			T3	22		T4	48		T5	17
valid_sources[0x43]	10798	1			T3	16		T4	16		T5	2
valid_sources[0x44]	11264	1			T3	15		T4	33		T5	11
valid_sources[0x45]	17201	1			T3	22		T4	32		T5	12
valid_sources[0x46]	10892	1			T1	1		T3	19		T4	38
valid_sources[0x47]	18542	1			T3	17		T4	22		T5	10
valid_sources[0x48]	11950	1			T3	18		T4	43		T5	14
valid_sources[0x49]	13725	1			T3	21		T4	23		T5	9
valid_sources[0x4a]	51771	1			T3	15		T4	15		T5	10
valid_sources[0x4b]	12724	1			T3	14		T4	25		T5	10
valid_sources[0x4c]	11307	1			T3	17		T4	35		T5	8
valid_sources[0x4d]	11238	1			T3	13		T4	32		T5	5
valid_sources[0x4e]	11473	1			T3	9		T4	35		T5	9
valid_sources[0x4f]	10532	1			T1	1		T3	24		T4	20
valid_sources[0x50]	10451	1			T3	14		T4	22		T5	11
valid_sources[0x51]	11213	1			T3	14		T4	19		T5	6
valid_sources[0x52]	21661	1			T3	16		T4	33		T5	8
valid_sources[0x53]	11174	1			T3	17		T4	30		T5	13
valid_sources[0x54]	10764	1			T3	13		T4	27		T5	15
valid_sources[0x55]	10459	1			T3	15		T4	43		T5	7
valid_sources[0x56]	12291	1			T3	16		T4	12		T5	8
valid_sources[0x57]	15074	1			T3	16		T4	27		T5	7
valid_sources[0x58]	15413	1			T3	21		T4	36		T5	13
valid_sources[0x59]	10517	1			T3	22		T4	27		T5	8
valid_sources[0x5a]	10768	1			T3	25		T4	21		T5	5
valid_sources[0x5b]	12820	1			T3	15		T4	36		T5	9
valid_sources[0x5c]	14777	1			T3	19		T4	21		T5	7
valid_sources[0x5d]	14686	1			T3	14		T4	24		T5	11
valid_sources[0x5e]	14896	1			T3	22		T4	38		T5	9
valid_sources[0x5f]	14702	1			T3	15		T4	28		T5	8
valid_sources[0x60]	10540	1			T3	14		T4	44		T5	10
valid_sources[0x61]	10506	1			T3	17		T4	21		T5	15
valid_sources[0x62]	10724	1			T3	18		T4	52		T5	10
valid_sources[0x63]	19837	1			T3	16		T4	23		T5	8
valid_sources[0x64]	11689	1			T3	20		T4	20		T5	12
valid_sources[0x65]	10363	1			T3	14		T4	22		T5	11
valid_sources[0x66]	11053	1			T3	24		T4	25		T5	10
valid_sources[0x67]	10832	1			T3	19		T4	23		T5	13
valid_sources[0x68]	53376	1			T3	17		T4	17		T5	10
valid_sources[0x69]	10657	1			T3	16		T4	16		T5	10
valid_sources[0x6a]	11895	1			T3	14		T4	23		T5	8
valid_sources[0x6b]	15646	1			T3	24		T4	24		T5	15
valid_sources[0x6c]	11609	1			T3	15		T4	34		T5	12
valid_sources[0x6d]	11861	1			T3	18		T4	26		T5	12
valid_sources[0x6e]	11802	1			T1	1		T3	17		T4	47
valid_sources[0x6f]	15361	1			T3	14		T4	28		T5	8
valid_sources[0x70]	11498	1			T3	16		T4	28		T5	9
valid_sources[0x71]	10244	1			T1	1		T3	19		T4	42
valid_sources[0x72]	17805	1			T3	14		T4	25		T5	11
valid_sources[0x73]	13216	1			T3	17		T4	27		T5	7
valid_sources[0x74]	11119	1			T3	21		T4	43		T5	10
valid_sources[0x75]	10850	1			T3	16		T4	34		T5	9
valid_sources[0x76]	15082	1			T3	20		T4	12		T5	8
valid_sources[0x77]	13394	1			T3	12		T4	20		T5	9
valid_sources[0x78]	10757	1			T3	18		T4	35		T5	12
valid_sources[0x79]	11755	1			T1	3		T3	11		T4	36
valid_sources[0x7a]	11077	1			T3	15		T4	29		T5	12
valid_sources[0x7b]	12141	1			T3	19		T4	8		T5	10
valid_sources[0x7c]	21616	1			T3	19		T4	30		T5	8
valid_sources[0x7d]	11504	1			T3	7		T4	32		T5	9
valid_sources[0x7e]	11127	1			T3	19		T4	21		T5	13
valid_sources[0x7f]	18491	1			T3	16		T4	16		T5	6
valid_sources[0x80]	10704	1			T3	17		T4	38		T5	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

344757

1

T1

1

T2

48

T3

1260

values[0x0]

all_enables

biggest_size

151341

1

T1

4

T2

16

T3

552

values[0x1]

all_enables

biggest_size

136846

1

T1

4

T2

7

T3

486