Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3447211	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

591545

1

T1

4

T2

175

T3

294

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3644253	1			T1	1		T2	17383		T3	415
values[0x0]	195898	1			T1	6		T2	69		T3	75
values[0x1]	198605	1			T1	4		T2	71		T3	83

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2356414	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1682342

1

T1

4

T2

5889

T3

357

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	22734	1			T4	18		T5	1		T16	35
valid_sources[0x01]	11431	1			T5	1		T16	47		T17	6
valid_sources[0x02]	15279	1			T5	9		T16	40		T17	14
valid_sources[0x03]	11815	1			T4	9		T5	9		T15	1
valid_sources[0x04]	13579	1			T5	5		T15	9		T16	35
valid_sources[0x05]	11881	1			T4	33		T5	5		T15	6
valid_sources[0x06]	13549	1			T4	4		T5	14		T15	1
valid_sources[0x07]	12463	1			T4	14		T5	3		T15	5
valid_sources[0x08]	12098	1			T15	2		T16	23		T17	13
valid_sources[0x09]	13091	1			T5	6		T15	3		T16	35
valid_sources[0x0a]	26265	1			T5	1		T16	39		T17	3
valid_sources[0x0b]	12840	1			T3	1		T5	18		T15	1
valid_sources[0x0c]	16115	1			T3	466		T4	9		T5	8
valid_sources[0x0d]	11634	1			T4	32		T5	1		T15	9
valid_sources[0x0e]	11812	1			T5	2		T16	44		T17	7
valid_sources[0x0f]	11308	1			T5	9		T16	42		T17	7
valid_sources[0x10]	11852	1			T5	4		T16	36		T17	14
valid_sources[0x11]	11834	1			T5	6		T15	6		T16	33
valid_sources[0x12]	11690	1			T5	18		T15	5		T16	34
valid_sources[0x13]	11247	1			T5	12		T15	4		T16	38
valid_sources[0x14]	18954	1			T5	18		T16	37		T17	6
valid_sources[0x15]	12672	1			T5	3		T14	5		T15	14
valid_sources[0x16]	11600	1			T16	49		T17	6		T38	433
valid_sources[0x17]	15089	1			T4	4		T15	1		T16	36
valid_sources[0x18]	15789	1			T5	19		T16	39		T17	3
valid_sources[0x19]	30454	1			T5	21		T16	33		T17	2
valid_sources[0x1a]	12213	1			T5	6		T15	2		T16	38
valid_sources[0x1b]	12319	1			T5	2		T15	3		T16	39
valid_sources[0x1c]	11592	1			T5	2		T15	5		T16	48
valid_sources[0x1d]	11314	1			T4	2		T5	3		T16	42
valid_sources[0x1e]	40539	1			T4	4		T5	2		T16	30
valid_sources[0x1f]	11415	1			T5	15		T15	5		T16	42
valid_sources[0x20]	12155	1			T5	6		T15	2		T16	31
valid_sources[0x21]	11755	1			T5	14		T15	2		T16	44
valid_sources[0x22]	12318	1			T5	1		T15	4		T16	27
valid_sources[0x23]	24952	1			T15	1		T16	34		T38	353
valid_sources[0x24]	13179	1			T4	2		T5	5		T15	3
valid_sources[0x25]	15002	1			T5	19		T15	2		T16	32
valid_sources[0x26]	11724	1			T5	3		T15	3		T16	36
valid_sources[0x27]	11789	1			T4	7		T5	19		T16	27
valid_sources[0x28]	12116	1			T4	2		T5	5		T14	3
valid_sources[0x29]	11350	1			T5	4		T15	6		T16	43
valid_sources[0x2a]	18428	1			T5	4		T15	5		T16	29
valid_sources[0x2b]	12305	1			T5	19		T16	53		T17	5
valid_sources[0x2c]	11666	1			T5	3		T15	9		T16	38
valid_sources[0x2d]	12378	1			T4	11		T5	7		T16	48
valid_sources[0x2e]	11292	1			T5	3		T16	48		T17	8
valid_sources[0x2f]	14776	1			T4	9		T5	14		T15	7
valid_sources[0x30]	11614	1			T4	9		T5	3		T15	4
valid_sources[0x31]	13511	1			T4	17		T5	4		T14	1
valid_sources[0x32]	12719	1			T4	14		T5	11		T16	29
valid_sources[0x33]	12774	1			T5	4		T16	30		T17	3
valid_sources[0x34]	16369	1			T5	1		T15	8		T16	33
valid_sources[0x35]	11410	1			T5	4		T14	1		T15	3
valid_sources[0x36]	15203	1			T5	8		T16	33		T17	11
valid_sources[0x37]	11436	1			T5	4		T16	37		T17	9
valid_sources[0x38]	11491	1			T5	8		T15	3		T16	49
valid_sources[0x39]	12435	1			T5	3		T15	3		T16	32
valid_sources[0x3a]	12474	1			T5	3		T15	7		T16	36
valid_sources[0x3b]	21088	1			T1	11		T4	9		T5	4
valid_sources[0x3c]	12555	1			T5	12		T15	1		T16	45
valid_sources[0x3d]	11047	1			T5	6		T16	47		T17	8
valid_sources[0x3e]	11496	1			T4	16		T5	1		T15	6
valid_sources[0x3f]	12034	1			T5	8		T15	3		T16	26
valid_sources[0x40]	22365	1			T4	24		T5	10		T15	3
valid_sources[0x41]	11898	1			T5	20		T15	4		T16	46
valid_sources[0x42]	13422	1			T4	5		T5	12		T15	6
valid_sources[0x43]	11340	1			T5	9		T16	47		T17	3
valid_sources[0x44]	11672	1			T5	9		T16	42		T17	3
valid_sources[0x45]	11595	1			T15	2		T16	46		T17	6
valid_sources[0x46]	22073	1			T4	9		T5	4		T15	2
valid_sources[0x47]	11244	1			T15	11		T16	35		T17	3
valid_sources[0x48]	11550	1			T5	6		T15	2		T16	39
valid_sources[0x49]	11441	1			T5	7		T15	2		T16	42
valid_sources[0x4a]	12301	1			T5	1		T15	7		T16	33
valid_sources[0x4b]	17392	1			T5	8		T15	2		T16	45
valid_sources[0x4c]	14501	1			T4	2		T5	6		T15	9
valid_sources[0x4d]	11638	1			T5	16		T15	1		T16	40
valid_sources[0x4e]	12965	1			T5	3		T16	46		T17	9
valid_sources[0x4f]	12545	1			T16	39		T17	3		T38	392
valid_sources[0x50]	11312	1			T5	6		T15	6		T16	41
valid_sources[0x51]	29321	1			T2	17523		T5	14		T15	1
valid_sources[0x52]	11353	1			T4	1		T5	7		T15	2
valid_sources[0x53]	11709	1			T5	1		T16	40		T17	5
valid_sources[0x54]	11434	1			T5	11		T15	2		T16	31
valid_sources[0x55]	13835	1			T4	9		T5	12		T16	35
valid_sources[0x56]	12309	1			T4	6		T5	17		T15	2
valid_sources[0x57]	11420	1			T4	41		T5	11		T15	4
valid_sources[0x58]	12770	1			T5	15		T16	30		T17	2
valid_sources[0x59]	11257	1			T5	9		T16	50		T17	4
valid_sources[0x5a]	12544	1			T4	1		T5	21		T14	1
valid_sources[0x5b]	13743	1			T4	3		T5	4		T15	2
valid_sources[0x5c]	11743	1			T5	6		T16	29		T17	7
valid_sources[0x5d]	27254	1			T4	2		T5	3		T15	12
valid_sources[0x5e]	12666	1			T5	7		T14	1		T15	12
valid_sources[0x5f]	13084	1			T5	6		T16	43		T17	6
valid_sources[0x60]	12024	1			T5	1		T15	16		T16	52
valid_sources[0x61]	13213	1			T5	5		T16	34		T17	1
valid_sources[0x62]	11980	1			T5	6		T15	4		T16	33
valid_sources[0x63]	12807	1			T4	11		T16	38		T17	2
valid_sources[0x64]	12151	1			T5	9		T15	1		T16	40
valid_sources[0x65]	18178	1			T4	41		T5	6		T15	14
valid_sources[0x66]	11029	1			T5	10		T14	2		T16	30
valid_sources[0x67]	11358	1			T5	21		T15	4		T16	31
valid_sources[0x68]	11302	1			T4	1		T5	10		T15	1
valid_sources[0x69]	12743	1			T5	6		T16	32		T17	6
valid_sources[0x6a]	11302	1			T4	3		T5	15		T15	1
valid_sources[0x6b]	12348	1			T4	34		T16	45		T17	4
valid_sources[0x6c]	12210	1			T5	1		T15	2		T16	42
valid_sources[0x6d]	11691	1			T5	14		T15	1		T16	28
valid_sources[0x6e]	12685	1			T5	9		T16	52		T17	4
valid_sources[0x6f]	10828	1			T5	4		T16	27		T17	1
valid_sources[0x70]	11233	1			T4	14		T5	12		T15	12
valid_sources[0x71]	17162	1			T5	11		T15	11		T16	39
valid_sources[0x72]	14931	1			T4	3		T5	5		T15	13
valid_sources[0x73]	11484	1			T4	7		T5	23		T16	37
valid_sources[0x74]	12510	1			T5	15		T16	31		T17	3
valid_sources[0x75]	11454	1			T5	7		T16	38		T17	3
valid_sources[0x76]	11203	1			T4	16		T5	3		T16	47
valid_sources[0x77]	11213	1			T5	17		T16	30		T17	8
valid_sources[0x78]	12338	1			T5	9		T16	46		T17	3
valid_sources[0x79]	15672	1			T5	3		T15	1		T16	32
valid_sources[0x7a]	13085	1			T4	1		T16	28		T17	7
valid_sources[0x7b]	11655	1			T4	20		T5	4		T14	2
valid_sources[0x7c]	12098	1			T4	6		T5	20		T16	34
valid_sources[0x7d]	11604	1			T5	11		T16	49		T17	5
valid_sources[0x7e]	10960	1			T5	2		T16	26		T17	6
valid_sources[0x7f]	11735	1			T15	1		T16	25		T17	3
valid_sources[0x80]	15055	1			T15	12		T16	38		T17	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

323771

1

T2

61

T3

194

T4

200

values[0x0]

all_enables

biggest_size

140720

1

T1

3

T2

56

T3

55

values[0x1]

all_enables

biggest_size

127054

1

T1

1

T2

58

T3

45