Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2584731	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

612787

1

T1

109

T2

148

T3

653

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2776198	1			T1	1482		T2	5859		T3	5644
values[0x0]	208543	1			T1	35		T2	45		T3	220
values[0x1]	212777	1			T1	37		T2	40		T3	214

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1779316	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1418202

1

T1

543

T2

2034

T3

2381

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12906	1			T1	7		T2	20		T3	1
valid_sources[0x01]	10294	1			T1	8		T2	20		T12	4
valid_sources[0x02]	11195	1			T1	3		T2	29		T3	29
valid_sources[0x03]	9992	1			T1	6		T2	21		T3	1
valid_sources[0x04]	11040	1			T1	5		T2	18		T3	7
valid_sources[0x05]	11416	1			T1	9		T2	23		T12	8
valid_sources[0x06]	20324	1			T1	6		T2	21		T3	95
valid_sources[0x07]	14468	1			T1	11		T2	29		T12	6
valid_sources[0x08]	13786	1			T1	5		T2	27		T12	10
valid_sources[0x09]	13834	1			T1	10		T2	18		T4	4
valid_sources[0x0a]	10689	1			T1	12		T2	24		T12	4
valid_sources[0x0b]	12668	1			T1	8		T2	20		T3	359
valid_sources[0x0c]	9582	1			T1	6		T2	19		T12	9
valid_sources[0x0d]	9981	1			T1	8		T2	26		T13	56
valid_sources[0x0e]	13442	1			T1	3		T2	12		T3	92
valid_sources[0x0f]	10114	1			T1	5		T2	19		T12	7
valid_sources[0x10]	10722	1			T1	2		T2	18		T12	2
valid_sources[0x11]	9490	1			T1	6		T2	33		T4	16
valid_sources[0x12]	11046	1			T1	10		T2	30		T3	4
valid_sources[0x13]	9317	1			T1	7		T2	32		T12	4
valid_sources[0x14]	11210	1			T1	6		T2	13		T12	15
valid_sources[0x15]	17012	1			T1	5		T2	20		T12	5
valid_sources[0x16]	12829	1			T1	8		T2	30		T3	5
valid_sources[0x17]	10659	1			T1	5		T2	26		T12	8
valid_sources[0x18]	14405	1			T1	3		T2	26		T4	1
valid_sources[0x19]	11411	1			T1	11		T2	17		T3	6
valid_sources[0x1a]	12193	1			T1	5		T2	24		T13	50
valid_sources[0x1b]	10532	1			T1	7		T2	26		T13	53
valid_sources[0x1c]	11412	1			T1	6		T2	31		T3	384
valid_sources[0x1d]	9601	1			T1	5		T2	30		T12	1
valid_sources[0x1e]	10545	1			T1	5		T2	22		T12	2
valid_sources[0x1f]	10176	1			T1	8		T2	26		T12	7
valid_sources[0x20]	12153	1			T1	6		T2	14		T11	521
valid_sources[0x21]	9714	1			T1	5		T2	33		T3	84
valid_sources[0x22]	9332	1			T1	10		T2	16		T4	5
valid_sources[0x23]	12979	1			T1	3		T2	26		T12	7
valid_sources[0x24]	11923	1			T1	6		T2	22		T13	37
valid_sources[0x25]	11252	1			T1	5		T2	20		T4	7
valid_sources[0x26]	10546	1			T1	6		T2	20		T12	16
valid_sources[0x27]	10071	1			T1	5		T2	24		T3	8
valid_sources[0x28]	9584	1			T1	5		T2	29		T4	3
valid_sources[0x29]	9822	1			T1	8		T2	27		T13	41
valid_sources[0x2a]	11415	1			T1	9		T2	26		T12	15
valid_sources[0x2b]	12739	1			T1	4		T2	20		T13	46
valid_sources[0x2c]	18840	1			T1	10		T2	20		T3	29
valid_sources[0x2d]	9719	1			T1	7		T2	27		T12	6
valid_sources[0x2e]	10777	1			T1	8		T2	23		T12	7
valid_sources[0x2f]	10353	1			T1	2		T2	19		T13	44
valid_sources[0x30]	11330	1			T1	3		T2	35		T13	65
valid_sources[0x31]	13912	1			T1	6		T2	19		T3	83
valid_sources[0x32]	10118	1			T1	11		T2	18		T3	23
valid_sources[0x33]	11005	1			T1	7		T2	17		T3	85
valid_sources[0x34]	11079	1			T1	1		T2	26		T3	93
valid_sources[0x35]	22007	1			T1	4		T2	21		T13	36
valid_sources[0x36]	10077	1			T1	7		T2	20		T3	1
valid_sources[0x37]	11291	1			T1	5		T2	28		T13	35
valid_sources[0x38]	13134	1			T1	7		T2	31		T4	2
valid_sources[0x39]	14274	1			T1	5		T2	21		T3	149
valid_sources[0x3a]	23652	1			T1	6		T2	29		T4	14
valid_sources[0x3b]	12011	1			T1	5		T2	24		T12	6
valid_sources[0x3c]	14909	1			T1	6		T2	25		T3	54
valid_sources[0x3d]	31079	1			T1	4		T2	33		T3	6
valid_sources[0x3e]	15566	1			T1	5		T2	23		T12	1
valid_sources[0x3f]	10010	1			T1	6		T2	30		T12	11
valid_sources[0x40]	11238	1			T1	9		T2	22		T12	27
valid_sources[0x41]	14068	1			T1	3		T2	27		T12	35
valid_sources[0x42]	25150	1			T1	6		T2	25		T4	3
valid_sources[0x43]	10078	1			T1	8		T2	30		T3	1
valid_sources[0x44]	14366	1			T1	2		T2	27		T12	9
valid_sources[0x45]	13976	1			T1	5		T2	23		T3	109
valid_sources[0x46]	16704	1			T1	8		T2	17		T4	33
valid_sources[0x47]	10396	1			T1	8		T2	19		T3	55
valid_sources[0x48]	10428	1			T1	7		T2	20		T3	1
valid_sources[0x49]	9646	1			T1	12		T2	12		T4	5
valid_sources[0x4a]	17043	1			T1	9		T2	20		T12	7
valid_sources[0x4b]	14548	1			T1	4		T2	18		T3	7
valid_sources[0x4c]	29287	1			T1	4		T2	21		T12	1
valid_sources[0x4d]	11189	1			T1	7		T2	20		T3	71
valid_sources[0x4e]	29456	1			T1	3		T2	19		T3	6
valid_sources[0x4f]	10662	1			T1	4		T2	21		T3	34
valid_sources[0x50]	12496	1			T1	9		T2	17		T3	640
valid_sources[0x51]	11949	1			T1	9		T2	27		T3	10
valid_sources[0x52]	14746	1			T1	5		T2	26		T12	12
valid_sources[0x53]	9789	1			T1	4		T2	24		T13	48
valid_sources[0x54]	11337	1			T1	6		T2	20		T3	155
valid_sources[0x55]	9238	1			T1	9		T2	29		T3	15
valid_sources[0x56]	21983	1			T1	3		T2	26		T12	1
valid_sources[0x57]	10653	1			T1	6		T2	26		T3	101
valid_sources[0x58]	10210	1			T1	8		T2	23		T3	16
valid_sources[0x59]	9812	1			T1	8		T2	27		T3	4
valid_sources[0x5a]	14438	1			T1	5		T2	31		T3	381
valid_sources[0x5b]	10372	1			T1	6		T2	26		T3	74
valid_sources[0x5c]	11471	1			T1	7		T2	26		T3	1
valid_sources[0x5d]	9703	1			T1	8		T2	26		T3	1
valid_sources[0x5e]	9690	1			T1	11		T2	14		T12	4
valid_sources[0x5f]	10257	1			T1	11		T2	17		T12	4
valid_sources[0x60]	12379	1			T1	5		T2	23		T12	4
valid_sources[0x61]	13533	1			T1	3		T2	18		T4	7
valid_sources[0x62]	10485	1			T1	7		T2	30		T12	1
valid_sources[0x63]	21330	1			T1	6		T2	29		T4	11
valid_sources[0x64]	16580	1			T1	5		T2	18		T3	9
valid_sources[0x65]	9697	1			T1	6		T2	20		T12	10
valid_sources[0x66]	10765	1			T1	11		T2	30		T13	43
valid_sources[0x67]	28673	1			T1	2		T2	31		T12	3
valid_sources[0x68]	10684	1			T1	6		T2	24		T3	2
valid_sources[0x69]	10512	1			T1	12		T2	33		T12	1
valid_sources[0x6a]	12902	1			T1	8		T2	29		T3	3
valid_sources[0x6b]	14693	1			T1	7		T2	26		T12	12
valid_sources[0x6c]	11708	1			T1	5		T2	22		T12	2
valid_sources[0x6d]	16806	1			T1	6		T2	16		T3	12
valid_sources[0x6e]	12908	1			T1	6		T2	28		T3	3
valid_sources[0x6f]	10379	1			T1	6		T2	19		T12	6
valid_sources[0x70]	12784	1			T1	9		T2	24		T3	410
valid_sources[0x71]	9689	1			T1	10		T2	24		T4	21
valid_sources[0x72]	11543	1			T1	6		T2	26		T13	54
valid_sources[0x73]	12327	1			T1	7		T2	18		T13	33
valid_sources[0x74]	9586	1			T1	7		T2	16		T12	5
valid_sources[0x75]	10006	1			T1	3		T2	19		T3	1
valid_sources[0x76]	10481	1			T1	4		T2	29		T4	22
valid_sources[0x77]	10697	1			T1	3		T2	25		T4	7
valid_sources[0x78]	12591	1			T1	4		T2	21		T12	6
valid_sources[0x79]	10208	1			T1	6		T2	23		T12	3
valid_sources[0x7a]	10483	1			T1	6		T2	28		T13	52
valid_sources[0x7b]	10250	1			T1	4		T2	23		T12	7
valid_sources[0x7c]	11806	1			T1	6		T2	35		T12	2
valid_sources[0x7d]	12825	1			T1	5		T2	27		T3	12
valid_sources[0x7e]	9801	1			T1	3		T2	23		T4	16
valid_sources[0x7f]	25472	1			T1	7		T2	11		T3	39
valid_sources[0x80]	14096	1			T1	5		T2	23		T13	57

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

324746

1

T1

70

T2

121

T3

352

values[0x0]

all_enables

biggest_size

150683

1

T1

23

T2

20

T3

164

values[0x1]

all_enables

biggest_size

137358

1

T1

16

T2

7

T3

137