Unified Coverage Report :: Module :: keymgr_data_en_state

Module : keymgr_data_en_state

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.78	93.33	33.33		88.89	83.33	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_data_en_state.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_ctrl.u_data_en	79.78	93.33	33.33		88.89	83.33	100.00

---

Module Instance : tb.dut.u_ctrl.u_data_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.78	93.33	33.33		88.89	83.33	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.42	94.87	33.33		88.89	85.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.62	100.00	98.11		100.00	100.00	100.00	u_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : keymgr_data_en_state

	Line No.	Total	Covered	Percent
TOTAL		30	28	93.33
ALWAYS	69	3	3	100.00
ALWAYS	79	27	25	92.59

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_data_en_state.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_data_en_state.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	3	3
79	1	1
80	1	1
81	1	1
82	1	1
83	1	1
86	1	1
87	1	1
88	1	1
89	1	1
90	1	1
91	1	1
92	1	1
93	0	1
			MISSING_ELSE
98	1	1
99	1	1
100	1	1
101	1	1
102	1	1
			MISSING_ELSE
107	1	1
108	1	1
109	1	1
110	1	1
111	0	1
			MISSING_ELSE
116	1	1
117	1	1
			MISSING_ELSE
122	1	1
123	1	1
			==> MISSING_ELSE

---

Cond Coverage for Module : keymgr_data_en_state

	Total	Covered	Percent
Conditions	3	1	33.33
Logical	3	1	33.33
Non-Logical	0	0
Event	0	0

 LINE       92
 EXPRESSION (id_en_i || gen_en_i)
             ---1---    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

---

FSM Coverage for Module : keymgr_data_en_state

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	9	8	88.89
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCtrlDataDis	87	Covered	T1,T2,T3
StCtrlDataHwEn	89	Covered	T2,T3,T4
StCtrlDataIdle	123	Covered	T1,T2,T3
StCtrlDataSwEn	91	Covered	T1,T3,T4
StCtrlDataWait	100	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StCtrlDataDis->StCtrlDataWait	117	Covered	T1,T2,T3
StCtrlDataHwEn->StCtrlDataDis	102	Covered	T5,T6,T7
StCtrlDataHwEn->StCtrlDataWait	100	Covered	T2,T3,T4
StCtrlDataIdle->StCtrlDataDis	87	Covered	T1,T2,T3
StCtrlDataIdle->StCtrlDataHwEn	89	Covered	T2,T3,T4
StCtrlDataIdle->StCtrlDataSwEn	91	Covered	T1,T3,T4
StCtrlDataSwEn->StCtrlDataDis	111	Not Covered
StCtrlDataSwEn->StCtrlDataWait	109	Covered	T1,T3,T4
StCtrlDataWait->StCtrlDataIdle	123	Covered	T1,T2,T3

---

Branch Coverage for Module : keymgr_data_en_state

	Line No.	Total	Covered	Percent
Branches		18	15	83.33
IF	69	2	2	100.00
CASE	83	16	13	81.25

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_data_en_state.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_data_en_state.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	83	case (state_q)
-2-:	86	if (adv_en_i)
-3-:	88	if (((id_en_i || gen_en_i) && prim_mubi_pkg::mubi4_test_true_strict(hw_sel_i)))
-4-:	90	if (((id_en_i || gen_en_i) && prim_mubi_pkg::mubi4_test_false_strict(hw_sel_i)))
-5-:	92	if ((id_en_i || gen_en_i))
-6-:	99	if (op_done_i)
-7-:	101	if ((adv_en_i || prim_mubi_pkg::mubi4_test_false_loose(hw_sel_i)))
-8-:	108	if (op_done_i)
-9-:	110	if ((adv_en_i || prim_mubi_pkg::mubi4_test_true_loose(hw_sel_i)))
-10-:	116	if (op_done_i)
-11-:	122	if ((!op_start_i))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	Status	Tests
StCtrlDataIdle	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StCtrlDataIdle	0	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
StCtrlDataIdle	0	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T4
StCtrlDataIdle	0	0	0	1	-	-	-	-	-	-	Not Covered
StCtrlDataIdle	0	0	0	0	-	-	-	-	-	-	Covered	T1,T2,T3
StCtrlDataHwEn	-	-	-	-	1	-	-	-	-	-	Covered	T2,T3,T4
StCtrlDataHwEn	-	-	-	-	0	1	-	-	-	-	Covered	T5,T6,T7
StCtrlDataHwEn	-	-	-	-	0	0	-	-	-	-	Covered	T2,T3,T4
StCtrlDataSwEn	-	-	-	-	-	-	1	-	-	-	Covered	T1,T3,T4
StCtrlDataSwEn	-	-	-	-	-	-	0	1	-	-	Not Covered
StCtrlDataSwEn	-	-	-	-	-	-	0	0	-	-	Covered	T1,T3,T4
StCtrlDataDis	-	-	-	-	-	-	-	-	1	-	Covered	T1,T2,T3
StCtrlDataDis	-	-	-	-	-	-	-	-	0	-	Covered	T1,T2,T3
StCtrlDataWait	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T3
StCtrlDataWait	-	-	-	-	-	-	-	-	-	0	Not Covered
default	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

---

Assert Coverage for Module : keymgr_data_en_state

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
u_state_regs_A	19261633	19103047	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19261633	19103047	0	0
T1	18468	18369	0	0
T2	68493	68438	0	0
T3	15579	15515	0	0
T4	4583	4509	0	0
T11	6510	6427	0	0
T12	13144	13090	0	0
T13	94087	94025	0	0
T14	2242	2084	0	0
T15	15996	15938	0	0
T16	8832	8713	0	0