Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2521755	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

635858

1

T1

195

T2

5

T3

2496

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2730182	1			T1	235		T2	1		T3	112151
values[0x0]	212099	1			T1	78		T2	14		T3	948
values[0x1]	215332	1			T1	101		T2	14		T3	940

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1742304	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1415309

1

T1

255

T2

6

T3

39582

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10917	1			T5	1		T12	9		T92	5
valid_sources[0x01]	10906	1			T1	414		T5	18		T12	4
valid_sources[0x02]	10752	1			T5	5		T11	855		T12	11
valid_sources[0x03]	8937	1			T4	6		T5	13		T12	21
valid_sources[0x04]	9953	1			T5	33		T12	13		T15	1
valid_sources[0x05]	9029	1			T4	4		T5	2		T12	13
valid_sources[0x06]	9558	1			T5	19		T12	31		T13	3
valid_sources[0x07]	10379	1			T5	17		T12	25		T13	1
valid_sources[0x08]	9161	1			T5	10		T12	10		T13	1
valid_sources[0x09]	10203	1			T4	4		T5	8		T12	15
valid_sources[0x0a]	10613	1			T5	9		T12	8		T13	2
valid_sources[0x0b]	10068	1			T4	25		T5	13		T12	24
valid_sources[0x0c]	11897	1			T5	10		T12	21		T92	8
valid_sources[0x0d]	11985	1			T5	16		T12	20		T13	2
valid_sources[0x0e]	9088	1			T5	16		T12	17		T13	1
valid_sources[0x0f]	9662	1			T2	1		T5	4		T12	14
valid_sources[0x10]	10489	1			T5	7		T12	23		T13	4
valid_sources[0x11]	10382	1			T5	15		T12	11		T13	1
valid_sources[0x12]	11473	1			T5	7		T12	8		T13	1
valid_sources[0x13]	9612	1			T5	10		T12	9		T13	2
valid_sources[0x14]	9762	1			T4	5		T5	11		T12	12
valid_sources[0x15]	11771	1			T4	12		T5	18		T12	16
valid_sources[0x16]	8762	1			T4	22		T5	29		T12	13
valid_sources[0x17]	9007	1			T4	10		T5	10		T12	14
valid_sources[0x18]	9298	1			T5	23		T12	16		T13	1
valid_sources[0x19]	9545	1			T5	6		T12	23		T13	1
valid_sources[0x1a]	13657	1			T5	5		T12	10		T13	3
valid_sources[0x1b]	9048	1			T4	7		T5	21		T12	31
valid_sources[0x1c]	10177	1			T5	8		T12	5		T13	1
valid_sources[0x1d]	9193	1			T5	15		T12	19		T15	1
valid_sources[0x1e]	8902	1			T4	6		T5	7		T12	10
valid_sources[0x1f]	9138	1			T5	8		T12	15		T92	1
valid_sources[0x20]	10369	1			T4	7		T5	16		T12	18
valid_sources[0x21]	14753	1			T5	14		T12	19		T13	2
valid_sources[0x22]	19423	1			T5	6		T12	17		T13	3
valid_sources[0x23]	9154	1			T5	16		T12	20		T92	8
valid_sources[0x24]	12967	1			T5	13		T12	9		T13	3
valid_sources[0x25]	10411	1			T5	1		T12	25		T13	1
valid_sources[0x26]	9060	1			T4	4		T5	16		T12	11
valid_sources[0x27]	15077	1			T4	1		T5	16		T12	12
valid_sources[0x28]	15791	1			T4	5		T5	15		T12	8
valid_sources[0x29]	12723	1			T5	7		T12	19		T13	3
valid_sources[0x2a]	10260	1			T5	14		T12	15		T71	2
valid_sources[0x2b]	9191	1			T5	20		T12	10		T71	5
valid_sources[0x2c]	15390	1			T5	6		T12	27		T13	3
valid_sources[0x2d]	10322	1			T4	4		T5	19		T12	17
valid_sources[0x2e]	15492	1			T5	26		T12	25		T13	1
valid_sources[0x2f]	9408	1			T2	4		T5	13		T12	11
valid_sources[0x30]	10977	1			T4	1		T5	18		T12	27
valid_sources[0x31]	9950	1			T5	5		T12	16		T71	1
valid_sources[0x32]	11847	1			T4	10		T5	7		T12	13
valid_sources[0x33]	9215	1			T4	2		T5	12		T12	13
valid_sources[0x34]	9607	1			T4	1		T5	15		T12	4
valid_sources[0x35]	10459	1			T5	14		T12	2		T13	3
valid_sources[0x36]	9911	1			T5	15		T12	15		T13	3
valid_sources[0x37]	9404	1			T4	24		T5	13		T12	23
valid_sources[0x38]	8585	1			T5	19		T12	10		T13	3
valid_sources[0x39]	9113	1			T5	13		T12	16		T13	4
valid_sources[0x3a]	9908	1			T4	10		T5	15		T12	23
valid_sources[0x3b]	10111	1			T4	14		T5	4		T12	15
valid_sources[0x3c]	11755	1			T5	32		T12	6		T13	1
valid_sources[0x3d]	11075	1			T4	1		T5	17		T12	13
valid_sources[0x3e]	9714	1			T5	16		T12	24		T13	1
valid_sources[0x3f]	9804	1			T5	13		T12	17		T13	3
valid_sources[0x40]	10243	1			T5	15		T12	9		T15	1
valid_sources[0x41]	9047	1			T5	9		T12	15		T13	4
valid_sources[0x42]	11972	1			T4	5		T5	12		T12	25
valid_sources[0x43]	9309	1			T4	1		T5	22		T12	21
valid_sources[0x44]	36082	1			T5	8		T12	13		T71	3
valid_sources[0x45]	13002	1			T5	11		T12	13		T13	1
valid_sources[0x46]	9762	1			T5	15		T12	4		T13	5
valid_sources[0x47]	15796	1			T5	20		T12	8		T13	3
valid_sources[0x48]	10464	1			T5	8		T12	16		T13	1
valid_sources[0x49]	10226	1			T4	7		T5	6		T12	16
valid_sources[0x4a]	15151	1			T4	1		T5	14		T12	17
valid_sources[0x4b]	9653	1			T5	15		T12	22		T13	3
valid_sources[0x4c]	26540	1			T5	8		T12	5		T13	1
valid_sources[0x4d]	21978	1			T5	7		T12	7		T13	1
valid_sources[0x4e]	9079	1			T4	15		T5	21		T12	18
valid_sources[0x4f]	8609	1			T5	15		T12	9		T13	1
valid_sources[0x50]	12328	1			T4	3		T5	24		T12	28
valid_sources[0x51]	8820	1			T4	1		T5	16		T12	8
valid_sources[0x52]	24868	1			T4	4		T5	13		T12	16
valid_sources[0x53]	9294	1			T5	18		T12	16		T13	1
valid_sources[0x54]	10622	1			T4	9		T5	12		T12	13
valid_sources[0x55]	10457	1			T5	21		T12	12		T13	1
valid_sources[0x56]	10260	1			T4	6		T5	14		T12	24
valid_sources[0x57]	9268	1			T4	3		T5	4		T12	33
valid_sources[0x58]	9374	1			T5	7		T12	19		T13	2
valid_sources[0x59]	9368	1			T4	18		T5	17		T12	20
valid_sources[0x5a]	10307	1			T5	20		T12	11		T13	7
valid_sources[0x5b]	9564	1			T5	28		T12	21		T71	3
valid_sources[0x5c]	10179	1			T4	1		T5	13		T12	12
valid_sources[0x5d]	9318	1			T4	8		T5	37		T12	16
valid_sources[0x5e]	9137	1			T4	1		T5	22		T12	27
valid_sources[0x5f]	12265	1			T5	22		T12	11		T13	2
valid_sources[0x60]	11094	1			T5	12		T12	23		T13	1
valid_sources[0x61]	10632	1			T5	22		T12	29		T13	3
valid_sources[0x62]	8949	1			T5	17		T12	14		T13	1
valid_sources[0x63]	8951	1			T5	6		T12	15		T13	1
valid_sources[0x64]	11722	1			T4	1		T5	17		T12	8
valid_sources[0x65]	9532	1			T4	9		T5	5		T12	5
valid_sources[0x66]	12780	1			T4	10		T5	5		T12	14
valid_sources[0x67]	9177	1			T4	24		T5	24		T12	17
valid_sources[0x68]	25587	1			T5	12		T12	7		T13	2
valid_sources[0x69]	17819	1			T5	15		T12	10		T13	2
valid_sources[0x6a]	9279	1			T5	13		T12	29		T15	3
valid_sources[0x6b]	10590	1			T4	2		T5	9		T12	12
valid_sources[0x6c]	9370	1			T4	12		T5	13		T12	9
valid_sources[0x6d]	12295	1			T5	12		T12	10		T13	1
valid_sources[0x6e]	10686	1			T5	17		T12	13		T13	2
valid_sources[0x6f]	8981	1			T4	8		T5	16		T12	7
valid_sources[0x70]	27798	1			T5	13		T12	11		T15	1
valid_sources[0x71]	12587	1			T2	4		T5	9		T12	18
valid_sources[0x72]	9339	1			T5	12		T12	13		T13	1
valid_sources[0x73]	10252	1			T5	20		T12	11		T13	3
valid_sources[0x74]	8902	1			T4	1		T5	14		T12	2
valid_sources[0x75]	11848	1			T5	15		T12	21		T13	4
valid_sources[0x76]	23342	1			T4	3		T5	14		T12	23
valid_sources[0x77]	9964	1			T4	16		T5	11		T12	4
valid_sources[0x78]	11120	1			T5	13		T12	15		T13	1
valid_sources[0x79]	8755	1			T5	16		T12	8		T13	2
valid_sources[0x7a]	9989	1			T5	17		T12	18		T13	1
valid_sources[0x7b]	10003	1			T5	21		T12	10		T13	3
valid_sources[0x7c]	12623	1			T5	11		T12	14		T13	5
valid_sources[0x7d]	9285	1			T5	17		T12	25		T15	1
valid_sources[0x7e]	9424	1			T5	25		T12	14		T13	1
valid_sources[0x7f]	9126	1			T5	7		T12	8		T13	1
valid_sources[0x80]	9460	1			T5	15		T12	34		T13	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

345648

1

T1

72

T3

1133

T4

239

values[0x0]

all_enables

biggest_size

152709

1

T1

55

T2

2

T3

709

values[0x1]

all_enables

biggest_size

137501

1

T1

68

T2

3

T3

654