Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
82 |
1 |
1 |
85 |
1 |
1 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
19673163 |
19509633 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19673163 |
19509633 |
0 |
0 |
T1 |
3893 |
3738 |
0 |
0 |
T2 |
1175 |
1100 |
0 |
0 |
T3 |
491934 |
491546 |
0 |
0 |
T4 |
3993 |
3862 |
0 |
0 |
T5 |
15689 |
15629 |
0 |
0 |
T11 |
7415 |
7357 |
0 |
0 |
T12 |
36801 |
36633 |
0 |
0 |
T13 |
2358 |
2290 |
0 |
0 |
T14 |
12302 |
12236 |
0 |
0 |
T15 |
5031 |
4854 |
0 |
0 |