Module Definition
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Module : keymgr_sideload_key_ctrl
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_sideload_key_ctrl.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_sideload_ctrl 100.00 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_sideload_ctrl

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.87 100.00 94.34 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.05 96.00 98.36 99.96 95.92 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_aes_key 95.83 100.00 87.50 100.00
u_kmac_key 95.83 100.00 87.50 100.00
u_mubi_buf 100.00 100.00 100.00
u_otbn_key 95.83 100.00 87.50 100.00
u_state_regs 100.00 100.00 100.00 100.00

Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : keymgr_sideload_key_ctrl
Line No.TotalCoveredPercent
TOTAL5050100.00
ALWAYS6633100.00
CONT_ASSIGN7111100.00
CONT_ASSIGN7111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8911100.00
ALWAYS921313100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14611100.00
ALWAYS19366100.00
ALWAYS19366100.00
ALWAYS19366100.00
CONT_ASSIGN20511100.00
CONT_ASSIGN20611100.00
CONT_ASSIGN20711100.00
CONT_ASSIGN21411100.00
CONT_ASSIGN21711100.00
CONT_ASSIGN22011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_sideload_key_ctrl.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_sideload_key_ctrl.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
66 3 3
71 2 2
78 1 1
84 1 1
85 1 1
86 1 1
89 1 1
92 1 1
93 1 1
94 1 1
96 1 1
98 1 1
99 1 1
MISSING_ELSE
106 1 1
107 1 1
108 1 1
MISSING_ELSE
113 1 1
114 1 1
115 1 1
MISSING_ELSE
121 1 1
144 1 1
145 1 1
146 1 1
193 1 1
194 1 1
195 1 1
196 1 1
197 1 1
198 1 1
MISSING_ELSE
193 1 1
194 1 1
195 1 1
196 1 1
197 1 1
198 1 1
MISSING_ELSE
193 1 1
194 1 1
195 1 1
196 1 1
197 1 1
198 1 1
MISSING_ELSE
205 1 1
206 1 1
207 1 1
214 1 1
217 1 1
220 1 1

Cond Coverage for Module : keymgr_sideload_key_ctrl
TotalCoveredPercent
Conditions2929100.00
Logical2929100.00
Non-Logical00
Event00

 LINE       78
 EXPRESSION (wipe_key_i | ((!(clr_key_i inside {SideLoadClrIdle, SideLoadClrAes, SideLoadClrKmac, SideLoadClrOtbn}))))
             -----1----   ---------------------------------------------2---------------------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T11
10CoveredT3,T4,T15 

 LINE       84
 EXPRESSION (clr_all_keys | (clr_key_i == SideLoadClrAes))
             ------1-----   --------------2--------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT3,T11,T12
10CoveredT1,T3,T4 

 LINE       84
 SUB-EXPRESSION (clr_key_i == SideLoadClrAes)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T11,T12 

 LINE       85
 EXPRESSION (clr_all_keys | (clr_key_i == SideLoadClrKmac))
             ------1-----   ---------------2--------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT3,T5,T11
10CoveredT1,T3,T4 

 LINE       85
 SUB-EXPRESSION (clr_key_i == SideLoadClrKmac)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T5,T11 

 LINE       86
 EXPRESSION (clr_all_keys | (clr_key_i == SideLoadClrOtbn))
             ------1-----   ---------------2--------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T5
10CoveredT1,T3,T4 

 LINE       86
 SUB-EXPRESSION (clr_key_i == SideLoadClrOtbn)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T5 

 LINE       148
 EXPRESSION (data_valid_i & slot_sel[AesIdx])
             ------1-----   --------2-------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T3,T4
11CoveredT3,T5,T13 

 LINE       163
 EXPRESSION (data_valid_i & slot_sel[OtbnIdx])
             ------1-----   --------2--------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T3,T4
11CoveredT1,T3,T11 

 LINE       177
 EXPRESSION (data_valid_i & slot_sel[KmacIdx])
             ------1-----   --------2--------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T3,T4
11CoveredT1,T3,T5 

 LINE       217
 EXPRESSION (key_i.valid ? key_i : kmac_sideload_key)
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4
FSM Coverage for Module : keymgr_sideload_key_ctrl
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 3 3 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StSideloadIdle 99 Covered T1,T3,T4
StSideloadReset 97 Covered T1,T2,T3
StSideloadStop 115 Covered T1,T3,T4
StSideloadWipe 108 Covered T1,T3,T4


transitionsLine No.CoveredTests
StSideloadIdle->StSideloadWipe 108 Covered T1,T3,T4
StSideloadReset->StSideloadIdle 99 Covered T1,T3,T4
StSideloadWipe->StSideloadStop 115 Covered T1,T3,T4


Branch Coverage for Module : keymgr_sideload_key_ctrl
Line No.TotalCoveredPercent
Branches 24 24 100.00
TERNARY 217 2 2 100.00
IF 66 2 2 100.00
CASE 96 8 8 100.00
IF 193 4 4 100.00
IF 193 4 4 100.00
IF 193 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_sideload_key_ctrl.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_sideload_key_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	217	(key_i.valid) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	66	if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	96	case (state_q)
-2-:	98	if (init_i)
-3-:	107	if (wipe_key_i)
-4-:	114	if ((!wipe_key_i))

Branches:
-1--2--3--4-StatusTests
StSideloadReset 1 - - Covered T1,T3,T4
StSideloadReset 0 - - Covered T1,T2,T3
StSideloadIdle - 1 - Covered T1,T3,T4
StSideloadIdle - 0 - Covered T1,T3,T4
StSideloadWipe - - 1 Covered T1,T3,T4
StSideloadWipe - - 0 Covered T1,T3,T4
StSideloadStop - - - Covered T1,T3,T4
default - - - Covered T8,T9,T10 



	LineNo.	Expression
-1-:	193	if ((!rst_ni))
-2-:	195	if (slot_clr[0])
-3-:	197	if (slot_sel[0])

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T3,T4
0 0 1 Covered T1,T3,T4
0 0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	193	if ((!rst_ni))
-2-:	195	if (slot_clr[1])
-3-:	197	if (slot_sel[1])

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T3,T4
0 0 1 Covered T1,T3,T4
0 0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	193	if ((!rst_ni))
-2-:	195	if (slot_clr[2])
-3-:	197	if (slot_sel[2])

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T3,T4
0 0 1 Covered T1,T3,T4
0 0 0 Covered T1,T2,T3

Assert Coverage for Module : keymgr_sideload_key_ctrl
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
KmacKeySource_a 19565988 11203 0 0
u_state_regs_A 19673163 19509633 0 0


KmacKeySource_a
NameAttemptsReal SuccessesFailuresIncomplete
Total 19565988 11203 0 0
T1 3893 4 0 0
T2 1175 0 0 0
T3 491934 68 0 0
T4 3993 2 0 0
T5 15689 13 0 0
T11 7415 8 0 0
T12 36801 20 0 0
T13 2358 8 0 0
T14 12302 16 0 0
T15 5031 0 0 0
T31 0 7 0 0
T70 0 7 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 19673163 19509633 0 0
T1 3893 3738 0 0
T2 1175 1100 0 0
T3 491934 491546 0 0
T4 3993 3862 0 0
T5 15689 15629 0 0
T11 7415 7357 0 0
T12 36801 36633 0 0
T13 2358 2290 0 0
T14 12302 12236 0 0
T15 5031 4854 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%