Unified Coverage Report :: Module :: keymgr_op_state_ctrl

Module : keymgr_op_state_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_op_state_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_ctrl.u_op_state	100.00	100.00	100.00		100.00	100.00	100.00

---

Module Instance : tb.dut.u_ctrl.u_op_state

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.62	100.00	98.11		100.00	100.00	100.00	u_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : keymgr_op_state_ctrl

	Line No.	Total	Covered	Percent
TOTAL		28	28	100.00
ALWAYS	44	3	3	100.00
CONT_ASSIGN	47	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	51	23	23	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_op_state_ctrl.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_op_state_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	3	3
47	1	1
48	1	1
51	1	1
52	1	1
53	1	1
54	1	1
57	1	1
59	1	1
60	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
			MISSING_ELSE
73	1	1
75	1	1
76		unreachable
77		unreachable
78	1	1
79	1	1
80	1	1
			MISSING_ELSE
86	1	1
91	1	1
93	1	1
94	1	1
95	1	1
			MISSING_ELSE

---

Cond Coverage for Module : keymgr_op_state_ctrl

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       47
 EXPRESSION (gen_en & id_req_i)
             ---1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       48
 EXPRESSION (gen_en & gen_req_i)
             ---1--   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       65
 EXPRESSION (adv_req_i || dis_req_i)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T71
1	0	Covered	T1,T3,T4

 LINE       67
 EXPRESSION (id_req_i || gen_req_i)
             ----1---    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       75
 EXPRESSION (kmac_done_i && (int'(cnt_i) == (keymgr_pkg::CDIs - 1)))
             -----1-----    -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Unreachable	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Unreachable	T1,T3,T4

 LINE       75
 SUB-EXPRESSION (int'(cnt_i) == (keymgr_pkg::CDIs - 1))
                -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Unreachable	T1,T3,T4

 LINE       78
 EXPRESSION (kmac_done_i && (int'(cnt_i) < (keymgr_pkg::CDIs - 1)))
             -----1-----    -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T1,T3,T4

---

FSM Coverage for Module : keymgr_op_state_ctrl

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StAdv	66	Covered	T1,T3,T4
StAdvAck	80	Covered	T1,T3,T4
StIdle	77	Covered	T1,T2,T3
StWait	68	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests
StAdv->StAdvAck	80	Covered	T1,T3,T4
StAdv->StIdle	77	Covered	T1,T3,T4
StAdvAck->StAdv	86	Covered	T1,T3,T4
StIdle->StAdv	66	Covered	T1,T3,T4
StIdle->StWait	68	Covered	T1,T3,T4
StWait->StIdle	95	Covered	T1,T3,T4

---

Branch Coverage for Module : keymgr_op_state_ctrl

	Line No.	Total	Covered	Percent
Branches		11	11	100.00
IF	44	2	2	100.00
CASE	62	9	9	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_op_state_ctrl.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_op_state_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	44	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	65	if ((adv_req_i || dis_req_i))
-3-:	67	if ((id_req_i || gen_req_i))
-4-:	75	if ((kmac_done_i && (int'(cnt_i) == (keymgr_pkg::CDIs - 1))))
-5-:	78	if ((kmac_done_i && (int'(cnt_i) < (keymgr_pkg::CDIs - 1))))
-6-:	93	if (kmac_done_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
StIdle	1	-	-	-	-	Covered	T1,T3,T4
StIdle	0	1	-	-	-	Covered	T1,T3,T4
StIdle	0	0	-	-	-	Covered	T1,T2,T3
StAdv	-	-	1	-	-	Unreachable	T1,T3,T4
StAdv	-	-	0	1	-	Covered	T1,T3,T4
StAdv	-	-	0	0	-	Covered	T1,T3,T4
StAdvAck	-	-	-	-	-	Covered	T1,T3,T4
StWait	-	-	-	-	1	Covered	T1,T3,T4
StWait	-	-	-	-	0	Covered	T1,T3,T4
default	-	-	-	-	-	Covered	T8,T9,T10

---

Assert Coverage for Module : keymgr_op_state_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
u_state_regs_A	19673163	19509633	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19673163	19509633	0	0
T1	3893	3738	0	0
T2	1175	1100	0	0
T3	491934	491546	0	0
T4	3993	3862	0	0
T5	15689	15629	0	0
T11	7415	7357	0	0
T12	36801	36633	0	0
T13	2358	2290	0	0
T14	12302	12236	0	0
T15	5031	4854	0	0