Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.05	96.00	98.36	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	21681767	14054	0	0
attest_sw_binding_0_rd_A	21681767	3538	0	0
attest_sw_binding_1_rd_A	21681767	3709	0	0
attest_sw_binding_2_rd_A	21681767	3683	0	0
attest_sw_binding_3_rd_A	21681767	3583	0	0
attest_sw_binding_4_rd_A	21681767	3731	0	0
attest_sw_binding_5_rd_A	21681767	3771	0	0
attest_sw_binding_6_rd_A	21681767	3827	0	0
attest_sw_binding_7_rd_A	21681767	3738	0	0
intr_enable_rd_A	21681767	4381	0	0
key_version_rd_A	21681767	3721	0	0
max_creator_key_ver_regwen_rd_A	21681767	3928	0	0
max_owner_int_key_ver_regwen_rd_A	21681767	3726	0	0
max_owner_key_ver_regwen_rd_A	21681767	3511	0	0
reseed_interval_regwen_rd_A	21681767	3870	0	0
salt_0_rd_A	21681767	3771	0	0
salt_1_rd_A	21681767	3738	0	0
salt_2_rd_A	21681767	3566	0	0
salt_3_rd_A	21681767	3772	0	0
salt_4_rd_A	21681767	3688	0	0
salt_5_rd_A	21681767	3699	0	0
salt_6_rd_A	21681767	3631	0	0
salt_7_rd_A	21681767	3740	0	0
sealing_sw_binding_0_rd_A	21681767	3684	0	0
sealing_sw_binding_1_rd_A	21681767	3717	0	0
sealing_sw_binding_2_rd_A	21681767	3762	0	0
sealing_sw_binding_3_rd_A	21681767	3737	0	0
sealing_sw_binding_4_rd_A	21681767	3655	0	0
sealing_sw_binding_5_rd_A	21681767	3803	0	0
sealing_sw_binding_6_rd_A	21681767	3778	0	0
sealing_sw_binding_7_rd_A	21681767	3824	0	0
sideload_clear_rd_A	21681767	3770	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21681767	14054	0	0
T12	36801	362	0	0
T13	2358	0	0	0
T14	12302	0	0	0
T15	5031	0	0	0
T31	67062	0	0	0
T36	0	817	0	0
T38	2729	0	0	0
T70	2349	0	0	0
T71	6866	0	0	0
T72	0	44	0	0
T77	0	63	0	0
T87	0	84	0	0
T88	0	46	0	0
T89	0	626	0	0
T90	0	1157	0	0
T91	0	790	0	0
T92	4381	0	0	0
T93	4472	0	0	0
T95	0	1131	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21681767	3538	0	0
T24	12085	0	0	0
T72	31659	19	0	0
T77	0	28	0	0
T96	6372	0	0	0
T109	0	32	0	0
T142	0	3	0	0
T160	0	70	0	0
T161	0	21	0	0
T162	0	25	0	0
T163	0	26	0	0
T164	0	52	0	0
T165	0	5	0	0
T166	9651	0	0	0
T167	13814	0	0	0
T168	17049	0	0	0
T169	9139	0	0	0
T170	2492	0	0	0
T171	15756	0	0	0
T172	8662	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21681767	3709	0	0
T24	12085	0	0	0
T72	31659	10	0	0
T77	0	46	0	0
T96	6372	0	0	0
T109	0	7	0	0
T142	0	6	0	0
T160	0	37	0	0
T161	0	16	0	0
T162	0	44	0	0
T163	0	19	0	0
T164	0	71	0	0
T165	0	10	0	0
T166	9651	0	0	0
T167	13814	0	0	0
T168	17049	0	0	0
T169	9139	0	0	0
T170	2492	0	0	0
T171	15756	0	0	0
T172	8662	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21681767	3683	0	0
T15	5031	1	0	0
T23	2617	0	0	0
T31	67062	0	0	0
T36	19993	0	0	0
T38	2729	0	0	0
T44	9545	0	0	0
T70	2349	0	0	0
T71	6866	0	0	0
T72	0	45	0	0
T77	0	19	0	0
T92	4381	0	0	0
T93	4472	0	0	0
T142	0	8	0	0
T160	0	43	0	0
T161	0	24	0	0
T162	0	36	0	0
T163	0	9	0	0
T164	0	54	0	0
T165	0	21	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21681767	3583	0	0
T24	12085	0	0	0
T72	31659	20	0	0
T77	0	24	0	0
T96	6372	0	0	0
T142	0	7	0	0
T160	0	74	0	0
T161	0	20	0	0
T162	0	36	0	0
T163	0	15	0	0
T164	0	64	0	0
T165	0	17	0	0
T166	9651	0	0	0
T167	13814	0	0	0
T168	17049	0	0	0
T169	9139	0	0	0
T170	2492	0	0	0
T171	15756	0	0	0
T172	8662	0	0	0
T173	0	6	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21681767	3731	0	0
T24	12085	0	0	0
T72	31659	21	0	0
T77	0	26	0	0
T96	6372	0	0	0
T109	0	20	0	0
T142	0	13	0	0
T160	0	49	0	0
T161	0	22	0	0
T162	0	25	0	0
T163	0	17	0	0
T164	0	44	0	0
T165	0	9	0	0
T166	9651	0	0	0
T167	13814	0	0	0
T168	17049	0	0	0
T169	9139	0	0	0
T170	2492	0	0	0
T171	15756	0	0	0
T172	8662	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21681767	3771	0	0
T24	12085	0	0	0
T72	31659	19	0	0
T77	0	32	0	0
T96	6372	0	0	0
T109	0	28	0	0
T142	0	7	0	0
T160	0	70	0	0
T161	0	42	0	0
T162	0	41	0	0
T163	0	20	0	0
T164	0	44	0	0
T165	0	5	0	0
T166	9651	0	0	0
T167	13814	0	0	0
T168	17049	0	0	0
T169	9139	0	0	0
T170	2492	0	0	0
T171	15756	0	0	0
T172	8662	0	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21681767	3827	0	0
T24	12085	0	0	0
T72	31659	30	0	0
T77	0	33	0	0
T96	6372	0	0	0
T109	0	6	0	0
T142	0	9	0	0
T160	0	73	0	0
T161	0	21	0	0
T162	0	38	0	0
T163	0	25	0	0
T164	0	57	0	0
T165	0	8	0	0
T166	9651	0	0	0
T167	13814	0	0	0
T168	17049	0	0	0
T169	9139	0	0	0
T170	2492	0	0	0
T171	15756	0	0	0
T172	8662	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21681767	3738	0	0
T24	12085	0	0	0
T72	31659	32	0	0
T77	0	28	0	0
T96	6372	0	0	0
T109	0	18	0	0
T142	0	10	0	0
T160	0	70	0	0
T161	0	18	0	0
T162	0	26	0	0
T163	0	12	0	0
T164	0	53	0	0
T165	0	14	0	0
T166	9651	0	0	0
T167	13814	0	0	0
T168	17049	0	0	0
T169	9139	0	0	0
T170	2492	0	0	0
T171	15756	0	0	0
T172	8662	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21681767	4381	0	0
T59	91661	64	0	0
T60	96980	0	0	0
T72	0	39	0	0
T77	0	33	0	0
T113	6785	0	0	0
T128	5252	0	0	0
T160	0	74	0	0
T174	0	19	0	0
T175	0	27	0	0
T176	0	19	0	0
T177	0	34	0	0
T178	0	15	0	0
T179	0	12	0	0
T180	3865	0	0	0
T181	23643	0	0	0
T182	4512	0	0	0
T183	101046	0	0	0
T184	4105	0	0	0
T185	4603	0	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21681767	3721	0	0
T34	7663	7	0	0
T35	1936	0	0	0
T72	31659	11	0	0
T77	0	25	0	0
T103	6332	0	0	0
T160	0	67	0	0
T161	0	28	0	0
T162	0	34	0	0
T163	0	32	0	0
T164	0	41	0	0
T165	0	14	0	0
T166	9651	0	0	0
T167	13814	0	0	0
T186	0	3	0	0
T187	18097	0	0	0
T188	23587	0	0	0
T189	16872	0	0	0
T190	5928	0	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21681767	3928	0	0
T24	12085	0	0	0
T72	31659	35	0	0
T77	0	26	0	0
T96	6372	0	0	0
T109	0	24	0	0
T142	0	11	0	0
T160	0	46	0	0
T161	0	29	0	0
T162	0	38	0	0
T163	0	9	0	0
T164	0	45	0	0
T165	0	9	0	0
T166	9651	0	0	0
T167	13814	0	0	0
T168	17049	0	0	0
T169	9139	0	0	0
T170	2492	0	0	0
T171	15756	0	0	0
T172	8662	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21681767	3726	0	0
T24	12085	0	0	0
T72	31659	29	0	0
T77	0	30	0	0
T96	6372	0	0	0
T142	0	9	0	0
T148	0	41	0	0
T160	0	40	0	0
T161	0	34	0	0
T162	0	16	0	0
T163	0	24	0	0
T164	0	40	0	0
T165	0	2	0	0
T166	9651	0	0	0
T167	13814	0	0	0
T168	17049	0	0	0
T169	9139	0	0	0
T170	2492	0	0	0
T171	15756	0	0	0
T172	8662	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21681767	3511	0	0
T24	12085	0	0	0
T72	31659	24	0	0
T77	0	32	0	0
T96	6372	0	0	0
T109	0	8	0	0
T142	0	4	0	0
T160	0	57	0	0
T161	0	15	0	0
T162	0	26	0	0
T163	0	33	0	0
T164	0	47	0	0
T165	0	5	0	0
T166	9651	0	0	0
T167	13814	0	0	0
T168	17049	0	0	0
T169	9139	0	0	0
T170	2492	0	0	0
T171	15756	0	0	0
T172	8662	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21681767	3870	0	0
T24	12085	0	0	0
T72	31659	32	0	0
T77	0	35	0	0
T96	6372	0	0	0
T109	0	24	0	0
T142	0	9	0	0
T160	0	71	0	0
T161	0	28	0	0
T162	0	40	0	0
T163	0	28	0	0
T164	0	28	0	0
T165	0	4	0	0
T166	9651	0	0	0
T167	13814	0	0	0
T168	17049	0	0	0
T169	9139	0	0	0
T170	2492	0	0	0
T171	15756	0	0	0
T172	8662	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21681767	3771	0	0
T24	12085	0	0	0
T72	31659	18	0	0
T77	0	36	0	0
T96	6372	0	0	0
T109	0	7	0	0
T142	0	4	0	0
T160	0	75	0	0
T161	0	21	0	0
T162	0	22	0	0
T163	0	23	0	0
T164	0	74	0	0
T165	0	21	0	0
T166	9651	0	0	0
T167	13814	0	0	0
T168	17049	0	0	0
T169	9139	0	0	0
T170	2492	0	0	0
T171	15756	0	0	0
T172	8662	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21681767	3738	0	0
T24	12085	0	0	0
T72	31659	37	0	0
T77	0	5	0	0
T96	6372	0	0	0
T109	0	35	0	0
T142	0	9	0	0
T160	0	73	0	0
T161	0	12	0	0
T162	0	19	0	0
T163	0	22	0	0
T164	0	60	0	0
T165	0	15	0	0
T166	9651	0	0	0
T167	13814	0	0	0
T168	17049	0	0	0
T169	9139	0	0	0
T170	2492	0	0	0
T171	15756	0	0	0
T172	8662	0	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21681767	3566	0	0
T24	12085	0	0	0
T72	31659	31	0	0
T77	0	25	0	0
T96	6372	0	0	0
T109	0	10	0	0
T142	0	7	0	0
T160	0	51	0	0
T161	0	40	0	0
T162	0	18	0	0
T163	0	15	0	0
T164	0	45	0	0
T165	0	15	0	0
T166	9651	0	0	0
T167	13814	0	0	0
T168	17049	0	0	0
T169	9139	0	0	0
T170	2492	0	0	0
T171	15756	0	0	0
T172	8662	0	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21681767	3772	0	0
T24	12085	0	0	0
T72	31659	12	0	0
T77	0	32	0	0
T96	6372	0	0	0
T109	0	39	0	0
T142	0	15	0	0
T160	0	83	0	0
T161	0	21	0	0
T162	0	29	0	0
T163	0	42	0	0
T164	0	46	0	0
T165	0	6	0	0
T166	9651	0	0	0
T167	13814	0	0	0
T168	17049	0	0	0
T169	9139	0	0	0
T170	2492	0	0	0
T171	15756	0	0	0
T172	8662	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21681767	3688	0	0
T24	12085	0	0	0
T72	31659	25	0	0
T77	0	17	0	0
T96	6372	0	0	0
T109	0	5	0	0
T142	0	5	0	0
T160	0	65	0	0
T161	0	27	0	0
T162	0	33	0	0
T163	0	32	0	0
T164	0	75	0	0
T165	0	6	0	0
T166	9651	0	0	0
T167	13814	0	0	0
T168	17049	0	0	0
T169	9139	0	0	0
T170	2492	0	0	0
T171	15756	0	0	0
T172	8662	0	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21681767	3699	0	0
T24	12085	0	0	0
T72	31659	20	0	0
T77	0	33	0	0
T96	6372	0	0	0
T109	0	1	0	0
T142	0	10	0	0
T160	0	76	0	0
T161	0	37	0	0
T162	0	41	0	0
T163	0	29	0	0
T164	0	38	0	0
T165	0	2	0	0
T166	9651	0	0	0
T167	13814	0	0	0
T168	17049	0	0	0
T169	9139	0	0	0
T170	2492	0	0	0
T171	15756	0	0	0
T172	8662	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21681767	3631	0	0
T24	12085	0	0	0
T72	31659	33	0	0
T77	0	43	0	0
T96	6372	0	0	0
T109	0	25	0	0
T142	0	9	0	0
T160	0	81	0	0
T161	0	21	0	0
T162	0	27	0	0
T163	0	24	0	0
T164	0	50	0	0
T165	0	12	0	0
T166	9651	0	0	0
T167	13814	0	0	0
T168	17049	0	0	0
T169	9139	0	0	0
T170	2492	0	0	0
T171	15756	0	0	0
T172	8662	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21681767	3740	0	0
T24	12085	0	0	0
T72	31659	23	0	0
T77	0	15	0	0
T96	6372	0	0	0
T109	0	13	0	0
T142	0	6	0	0
T160	0	60	0	0
T161	0	23	0	0
T162	0	27	0	0
T163	0	22	0	0
T164	0	51	0	0
T165	0	31	0	0
T166	9651	0	0	0
T167	13814	0	0	0
T168	17049	0	0	0
T169	9139	0	0	0
T170	2492	0	0	0
T171	15756	0	0	0
T172	8662	0	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21681767	3684	0	0
T24	12085	0	0	0
T72	31659	15	0	0
T77	0	30	0	0
T96	6372	0	0	0
T109	0	7	0	0
T142	0	7	0	0
T160	0	50	0	0
T161	0	29	0	0
T162	0	16	0	0
T163	0	30	0	0
T164	0	48	0	0
T165	0	12	0	0
T166	9651	0	0	0
T167	13814	0	0	0
T168	17049	0	0	0
T169	9139	0	0	0
T170	2492	0	0	0
T171	15756	0	0	0
T172	8662	0	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21681767	3717	0	0
T24	12085	0	0	0
T72	31659	15	0	0
T77	0	21	0	0
T96	6372	0	0	0
T142	0	1	0	0
T160	0	65	0	0
T161	0	46	0	0
T162	0	35	0	0
T163	0	22	0	0
T164	0	40	0	0
T165	0	25	0	0
T166	9651	0	0	0
T167	13814	0	0	0
T168	17049	0	0	0
T169	9139	0	0	0
T170	2492	0	0	0
T171	15756	0	0	0
T172	8662	0	0	0
T191	0	5	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21681767	3762	0	0
T24	12085	0	0	0
T72	31659	21	0	0
T77	0	36	0	0
T96	6372	0	0	0
T142	0	16	0	0
T160	0	76	0	0
T161	0	18	0	0
T162	0	41	0	0
T163	0	34	0	0
T164	0	39	0	0
T165	0	10	0	0
T166	9651	0	0	0
T167	13814	0	0	0
T168	17049	0	0	0
T169	9139	0	0	0
T170	2492	0	0	0
T171	15756	0	0	0
T172	8662	0	0	0
T192	0	5	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21681767	3737	0	0
T24	12085	0	0	0
T72	31659	16	0	0
T77	0	19	0	0
T96	6372	0	0	0
T109	0	40	0	0
T142	0	10	0	0
T160	0	52	0	0
T161	0	19	0	0
T162	0	47	0	0
T163	0	20	0	0
T164	0	45	0	0
T165	0	4	0	0
T166	9651	0	0	0
T167	13814	0	0	0
T168	17049	0	0	0
T169	9139	0	0	0
T170	2492	0	0	0
T171	15756	0	0	0
T172	8662	0	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21681767	3655	0	0
T24	12085	0	0	0
T72	31659	17	0	0
T77	0	22	0	0
T96	6372	0	0	0
T142	0	3	0	0
T148	0	50	0	0
T160	0	71	0	0
T161	0	28	0	0
T162	0	24	0	0
T163	0	19	0	0
T164	0	45	0	0
T165	0	9	0	0
T166	9651	0	0	0
T167	13814	0	0	0
T168	17049	0	0	0
T169	9139	0	0	0
T170	2492	0	0	0
T171	15756	0	0	0
T172	8662	0	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21681767	3803	0	0
T24	12085	0	0	0
T72	31659	34	0	0
T77	0	23	0	0
T96	6372	0	0	0
T109	0	13	0	0
T142	0	6	0	0
T160	0	65	0	0
T161	0	20	0	0
T162	0	36	0	0
T163	0	25	0	0
T164	0	61	0	0
T165	0	18	0	0
T166	9651	0	0	0
T167	13814	0	0	0
T168	17049	0	0	0
T169	9139	0	0	0
T170	2492	0	0	0
T171	15756	0	0	0
T172	8662	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21681767	3778	0	0
T24	12085	0	0	0
T72	31659	27	0	0
T77	0	26	0	0
T96	6372	0	0	0
T109	0	15	0	0
T142	0	8	0	0
T160	0	46	0	0
T161	0	44	0	0
T162	0	30	0	0
T163	0	23	0	0
T164	0	38	0	0
T165	0	27	0	0
T166	9651	0	0	0
T167	13814	0	0	0
T168	17049	0	0	0
T169	9139	0	0	0
T170	2492	0	0	0
T171	15756	0	0	0
T172	8662	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21681767	3824	0	0
T24	12085	0	0	0
T72	31659	15	0	0
T77	0	18	0	0
T96	6372	0	0	0
T109	0	18	0	0
T142	0	4	0	0
T160	0	75	0	0
T161	0	14	0	0
T162	0	22	0	0
T163	0	32	0	0
T164	0	55	0	0
T165	0	29	0	0
T166	9651	0	0	0
T167	13814	0	0	0
T168	17049	0	0	0
T169	9139	0	0	0
T170	2492	0	0	0
T171	15756	0	0	0
T172	8662	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21681767	3770	0	0
T24	12085	0	0	0
T72	31659	23	0	0
T77	0	35	0	0
T96	6372	0	0	0
T109	0	36	0	0
T142	0	8	0	0
T160	0	47	0	0
T161	0	22	0	0
T162	0	21	0	0
T163	0	8	0	0
T164	0	66	0	0
T165	0	13	0	0
T166	9651	0	0	0
T167	13814	0	0	0
T168	17049	0	0	0
T169	9139	0	0	0
T170	2492	0	0	0
T171	15756	0	0	0
T172	8662	0	0	0