Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2433309	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

586943

1

T1

231

T2

151

T3

131

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2626899	1			T1	13426		T2	2428		T3	1552
values[0x0]	194692	1			T1	66		T2	35		T3	41
values[0x1]	198661	1			T1	63		T2	57		T3	48

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1678309	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1341943

1

T1

4704

T2

908

T3

604

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9456	1			T1	72		T2	3		T3	9
valid_sources[0x01]	11929	1			T1	48		T2	4		T3	2
valid_sources[0x02]	11313	1			T1	51		T2	5		T3	9
valid_sources[0x03]	8501	1			T1	32		T2	15		T3	17
valid_sources[0x04]	10775	1			T1	51		T2	12		T3	11
valid_sources[0x05]	8902	1			T1	53		T2	26		T3	5
valid_sources[0x06]	9468	1			T1	45		T2	18		T3	4
valid_sources[0x07]	9790	1			T1	48		T2	8		T3	6
valid_sources[0x08]	9814	1			T1	53		T2	14		T3	3
valid_sources[0x09]	9661	1			T1	60		T2	7		T3	7
valid_sources[0x0a]	9229	1			T1	38		T2	4		T3	11
valid_sources[0x0b]	9886	1			T1	37		T2	11		T3	10
valid_sources[0x0c]	17782	1			T1	57		T2	7		T3	1
valid_sources[0x0d]	9354	1			T1	43		T2	20		T3	5
valid_sources[0x0e]	9543	1			T1	40		T2	5		T3	13
valid_sources[0x0f]	9199	1			T1	37		T2	14		T3	7
valid_sources[0x10]	10295	1			T1	51		T2	5		T3	2
valid_sources[0x11]	11958	1			T1	67		T2	17		T3	7
valid_sources[0x12]	10579	1			T1	48		T2	6		T3	11
valid_sources[0x13]	8945	1			T1	42		T2	14		T3	3
valid_sources[0x14]	9987	1			T1	54		T2	2		T3	10
valid_sources[0x15]	9360	1			T1	66		T2	8		T3	8
valid_sources[0x16]	8801	1			T1	68		T2	11		T3	6
valid_sources[0x17]	15501	1			T1	40		T2	8		T3	10
valid_sources[0x18]	11835	1			T1	45		T2	7		T3	6
valid_sources[0x19]	14388	1			T1	42		T2	13		T3	3
valid_sources[0x1a]	9156	1			T1	52		T2	9		T3	14
valid_sources[0x1b]	9180	1			T1	56		T2	5		T3	6
valid_sources[0x1c]	14484	1			T1	51		T2	2		T3	9
valid_sources[0x1d]	16959	1			T1	36		T2	21		T3	12
valid_sources[0x1e]	8808	1			T1	49		T2	9		T3	2
valid_sources[0x1f]	8898	1			T1	46		T2	3		T3	17
valid_sources[0x20]	11557	1			T1	56		T2	5		T3	3
valid_sources[0x21]	9572	1			T1	40		T2	9		T3	3
valid_sources[0x22]	9142	1			T1	52		T2	7		T3	11
valid_sources[0x23]	9117	1			T1	62		T2	12		T3	2
valid_sources[0x24]	9392	1			T1	50		T2	5		T3	2
valid_sources[0x25]	8997	1			T1	63		T2	17		T3	8
valid_sources[0x26]	10818	1			T1	58		T2	16		T3	1
valid_sources[0x27]	11194	1			T1	46		T2	6		T3	6
valid_sources[0x28]	10675	1			T1	77		T2	9		T3	4
valid_sources[0x29]	9062	1			T1	51		T2	8		T3	10
valid_sources[0x2a]	11364	1			T1	49		T2	24		T3	7
valid_sources[0x2b]	16581	1			T1	59		T2	11		T3	9
valid_sources[0x2c]	10672	1			T1	41		T2	10		T3	7
valid_sources[0x2d]	10908	1			T1	56		T2	9		T3	14
valid_sources[0x2e]	9932	1			T1	119		T2	22		T3	6
valid_sources[0x2f]	15748	1			T1	61		T2	11		T3	3
valid_sources[0x30]	9313	1			T1	55		T2	10		T3	7
valid_sources[0x31]	9307	1			T1	56		T2	4		T3	2
valid_sources[0x32]	8876	1			T1	50		T2	10		T3	6
valid_sources[0x33]	9310	1			T1	60		T2	20		T3	11
valid_sources[0x34]	9252	1			T1	51		T2	7		T3	9
valid_sources[0x35]	9167	1			T1	44		T2	11		T3	10
valid_sources[0x36]	9862	1			T1	73		T2	11		T3	1
valid_sources[0x37]	11430	1			T1	51		T2	13		T3	1
valid_sources[0x38]	9604	1			T1	53		T2	15		T3	5
valid_sources[0x39]	14556	1			T1	44		T2	15		T3	7
valid_sources[0x3a]	9361	1			T1	56		T2	13		T3	6
valid_sources[0x3b]	11421	1			T1	29		T2	16		T3	6
valid_sources[0x3c]	10934	1			T1	53		T2	10		T3	12
valid_sources[0x3d]	8620	1			T1	35		T2	14		T3	6
valid_sources[0x3e]	10119	1			T1	68		T2	10		T3	2
valid_sources[0x3f]	9345	1			T1	53		T2	1		T3	6
valid_sources[0x40]	10537	1			T1	61		T2	6		T3	11
valid_sources[0x41]	9129	1			T1	47		T2	15		T3	16
valid_sources[0x42]	9408	1			T1	67		T2	9		T3	3
valid_sources[0x43]	13251	1			T1	57		T2	6		T3	2
valid_sources[0x44]	10815	1			T1	68		T2	9		T3	12
valid_sources[0x45]	12893	1			T1	55		T2	13		T3	5
valid_sources[0x46]	11155	1			T1	58		T2	6		T3	4
valid_sources[0x47]	11455	1			T1	49		T2	8		T3	12
valid_sources[0x48]	9820	1			T1	49		T2	8		T3	7
valid_sources[0x49]	11115	1			T1	41		T2	17		T3	3
valid_sources[0x4a]	9096	1			T1	58		T2	6		T3	6
valid_sources[0x4b]	10305	1			T1	71		T2	4		T3	4
valid_sources[0x4c]	10678	1			T1	64		T2	13		T3	7
valid_sources[0x4d]	8866	1			T1	67		T2	9		T3	5
valid_sources[0x4e]	10130	1			T1	48		T2	2		T3	3
valid_sources[0x4f]	15287	1			T1	54		T3	7		T4	5
valid_sources[0x50]	23011	1			T1	68		T2	11		T3	11
valid_sources[0x51]	10437	1			T1	39		T2	6		T3	9
valid_sources[0x52]	23777	1			T1	44		T2	13		T3	3
valid_sources[0x53]	11354	1			T1	51		T2	16		T3	9
valid_sources[0x54]	9419	1			T1	44		T2	3		T3	14
valid_sources[0x55]	11808	1			T1	56		T2	7		T3	13
valid_sources[0x56]	10968	1			T1	60		T2	4		T3	2
valid_sources[0x57]	9634	1			T1	40		T2	17		T3	6
valid_sources[0x58]	9144	1			T1	71		T2	13		T3	7
valid_sources[0x59]	9360	1			T1	68		T2	5		T3	3
valid_sources[0x5a]	10150	1			T1	53		T2	8		T3	2
valid_sources[0x5b]	21234	1			T1	43		T2	21		T3	2
valid_sources[0x5c]	17952	1			T1	58		T2	7		T3	9
valid_sources[0x5d]	21697	1			T1	67		T2	14		T3	2
valid_sources[0x5e]	10523	1			T1	38		T2	14		T3	6
valid_sources[0x5f]	8971	1			T1	55		T2	18		T3	2
valid_sources[0x60]	9935	1			T1	60		T2	10		T3	4
valid_sources[0x61]	9211	1			T1	49		T2	7		T3	1
valid_sources[0x62]	25341	1			T1	50		T2	10		T3	8
valid_sources[0x63]	8887	1			T1	65		T2	9		T3	7
valid_sources[0x64]	9230	1			T1	42		T2	6		T3	4
valid_sources[0x65]	10428	1			T1	42		T2	11		T3	2
valid_sources[0x66]	21520	1			T1	44		T2	2		T3	10
valid_sources[0x67]	15263	1			T1	52		T2	22		T3	6
valid_sources[0x68]	10959	1			T1	43		T2	12		T3	8
valid_sources[0x69]	11284	1			T1	61		T2	10		T3	10
valid_sources[0x6a]	10463	1			T1	55		T2	13		T3	5
valid_sources[0x6b]	8905	1			T1	39		T2	12		T3	1
valid_sources[0x6c]	9398	1			T1	57		T2	16		T3	6
valid_sources[0x6d]	9276	1			T1	58		T2	3		T3	5
valid_sources[0x6e]	9592	1			T1	82		T2	5		T3	10
valid_sources[0x6f]	12715	1			T1	53		T2	14		T3	4
valid_sources[0x70]	9212	1			T1	44		T2	5		T3	5
valid_sources[0x71]	11843	1			T1	48		T2	8		T3	9
valid_sources[0x72]	8913	1			T1	56		T2	7		T3	9
valid_sources[0x73]	9517	1			T1	74		T2	14		T3	3
valid_sources[0x74]	13581	1			T1	50		T2	12		T3	5
valid_sources[0x75]	9494	1			T1	61		T2	32		T3	5
valid_sources[0x76]	11953	1			T1	77		T2	5		T3	8
valid_sources[0x77]	8850	1			T1	76		T2	3		T3	3
valid_sources[0x78]	9854	1			T1	54		T2	14		T3	6
valid_sources[0x79]	8788	1			T1	56		T2	14		T3	2
valid_sources[0x7a]	8807	1			T1	55		T2	7		T3	6
valid_sources[0x7b]	9499	1			T1	53		T2	12		T3	8
valid_sources[0x7c]	8952	1			T1	56		T2	2		T3	4
valid_sources[0x7d]	8919	1			T1	57		T2	4		T3	4
valid_sources[0x7e]	10019	1			T1	74		T2	22		T3	3
valid_sources[0x7f]	8401	1			T1	51		T3	14		T6	7
valid_sources[0x80]	17668	1			T1	59		T2	7		T3	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

320227

1

T1

202

T2

124

T3

107

values[0x0]

all_enables

biggest_size

139879

1

T1

18

T2

12

T3

12

values[0x1]

all_enables

biggest_size

126837

1

T1

11

T2

15

T3

12