Unified Coverage Report :: Module :: prim_msb_extend

Module : prim_msb_extend

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_msb_extend_0/rtl/prim_msb_extend.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_checks.u_creator_seed	100.00	100.00					100.00
tb.dut.u_checks.u_owner_seed	100.00	100.00					100.00
tb.dut.u_checks.u_devid	100.00	100.00					100.00
tb.dut.u_checks.u_health_state	100.00	100.00					100.00
tb.dut.u_checks.gen_key_chk[0].u_key_pad	100.00	100.00					100.00
tb.dut.u_checks.gen_key_chk[1].u_key_pad	100.00	100.00					100.00

---

Module Instance : tb.dut.u_checks.u_creator_seed

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_checks

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_checks.u_owner_seed

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_checks

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_checks.u_devid

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_checks

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_checks.u_health_state

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_checks

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_checks.gen_key_chk[0].u_key_pad

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_checks

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_checks.gen_key_chk[1].u_key_pad

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_checks

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_msb_extend ( parameter InWidth=256,OutWidth=256,WidthDiff=0 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_checks.u_creator_seed

SCORE	LINE
100.00	100.00

tb.dut.u_checks.u_owner_seed

SCORE	LINE
100.00	100.00

tb.dut.u_checks.u_devid

SCORE	LINE
100.00	100.00

tb.dut.u_checks.gen_key_chk[0].u_key_pad

SCORE	LINE
100.00	100.00

tb.dut.u_checks.gen_key_chk[1].u_key_pad

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	22	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_msb_extend_0/rtl/prim_msb_extend.sv' or '../src/lowrisc_prim_msb_extend_0/rtl/prim_msb_extend.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
22	1	1

---

Line Coverage for Module : prim_msb_extend ( parameter InWidth=128,OutWidth=256,WidthDiff=128 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_checks.u_health_state

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_msb_extend_0/rtl/prim_msb_extend.sv' or '../src/lowrisc_prim_msb_extend_0/rtl/prim_msb_extend.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Assert Coverage for Module : prim_msb_extend

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
WidthCheck_A	5244	5244	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5244	5244	0	0
T1	6	6	0	0
T2	6	6	0	0
T3	6	6	0	0
T4	6	6	0	0
T5	6	6	0	0
T6	6	6	0	0
T12	6	6	0	0
T15	6	6	0	0
T16	6	6	0	0
T17	6	6	0	0

Line Coverage for Instance : tb.dut.u_checks.u_creator_seed

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	22	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_msb_extend_0/rtl/prim_msb_extend.sv' or '../src/lowrisc_prim_msb_extend_0/rtl/prim_msb_extend.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
22	1	1

---

Assert Coverage for Instance : tb.dut.u_checks.u_creator_seed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
WidthCheck_A	874	874	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874	874	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_checks.u_owner_seed

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	22	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_msb_extend_0/rtl/prim_msb_extend.sv' or '../src/lowrisc_prim_msb_extend_0/rtl/prim_msb_extend.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
22	1	1

---

Assert Coverage for Instance : tb.dut.u_checks.u_owner_seed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
WidthCheck_A	874	874	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874	874	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_checks.u_devid

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	22	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_msb_extend_0/rtl/prim_msb_extend.sv' or '../src/lowrisc_prim_msb_extend_0/rtl/prim_msb_extend.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
22	1	1

---

Assert Coverage for Instance : tb.dut.u_checks.u_devid

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
WidthCheck_A	874	874	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874	874	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_checks.u_health_state

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_msb_extend_0/rtl/prim_msb_extend.sv' or '../src/lowrisc_prim_msb_extend_0/rtl/prim_msb_extend.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Assert Coverage for Instance : tb.dut.u_checks.u_health_state

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
WidthCheck_A	874	874	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874	874	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_checks.gen_key_chk[0].u_key_pad

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	22	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_msb_extend_0/rtl/prim_msb_extend.sv' or '../src/lowrisc_prim_msb_extend_0/rtl/prim_msb_extend.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
22	1	1

---

Assert Coverage for Instance : tb.dut.u_checks.gen_key_chk[0].u_key_pad

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
WidthCheck_A	874	874	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874	874	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_checks.gen_key_chk[1].u_key_pad

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	22	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_msb_extend_0/rtl/prim_msb_extend.sv' or '../src/lowrisc_prim_msb_extend_0/rtl/prim_msb_extend.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
22	1	1

---

Assert Coverage for Instance : tb.dut.u_checks.gen_key_chk[1].u_key_pad

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
WidthCheck_A	874	874	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874	874	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0