Unified Coverage Report :: Module :: keymgr_sideload_key

Module : keymgr_sideload_key

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.83	100.00	87.50			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_sideload_key.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sideload_ctrl.u_aes_key	95.83	100.00	87.50			100.00
tb.dut.u_sideload_ctrl.u_otbn_key	95.83	100.00	87.50			100.00
tb.dut.u_sideload_ctrl.u_kmac_key	95.83	100.00	87.50			100.00

---

Module Instance : tb.dut.u_sideload_ctrl.u_aes_key

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.83	100.00	87.50			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.83	100.00	87.50			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00		100.00	100.00	100.00	u_sideload_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sideload_ctrl.u_otbn_key

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.83	100.00	87.50			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.83	100.00	87.50			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00		100.00	100.00	100.00	u_sideload_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sideload_ctrl.u_kmac_key

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.83	100.00	87.50			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.83	100.00	87.50			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00		100.00	100.00	100.00	u_sideload_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : keymgr_sideload_key

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
ALWAYS	33	6	6	100.00
ALWAYS	43	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_sideload_key.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_sideload_key.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	1	1
30	1	1
33	1	1
34	1	1
35	1	1
36	1	1
37	1	1
38	1	1
			MISSING_ELSE
43	1	1
44	1	1
45	1	1
46	1	1
47	1	1
49	1	1
50	1	1
51	1	1
			MISSING_ELSE

---

Cond Coverage for Module : keymgr_sideload_key ( parameter Width=256,EntropyCopies=8 )
Cond Coverage for Module self-instances :

SCORE	COND
95.83	87.50

tb.dut.u_sideload_ctrl.u_aes_key

SCORE	COND
95.83	87.50

tb.dut.u_sideload_ctrl.u_kmac_key

	Total	Covered	Percent
Conditions	8	7	87.50
Logical	8	7	87.50
Non-Logical	0	0
Event	0	0

 LINE       29
 EXPRESSION (valid_q & en_i)
             ---1---   --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T17

 LINE       35
 EXPRESSION (((!en_i)) || clr_i)
             ----1----    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       51
 EXPRESSION (set_en_i ? key_i[i] : ({EntropyCopies {entropy_i[i]}}))
             ----1---

-1-	Status	Tests
0	Covered	T14,T43
1	Covered	T2,T4,T17

---

Cond Coverage for Module : keymgr_sideload_key ( parameter Width=384,EntropyCopies=12 )
Cond Coverage for Module self-instances :

SCORE	COND
95.83	87.50

tb.dut.u_sideload_ctrl.u_otbn_key

	Total	Covered	Percent
Conditions	8	7	87.50
Logical	8	7	87.50
Non-Logical	0	0
Event	0	0

 LINE       29
 EXPRESSION (valid_q & en_i)
             ---1---   --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T16

 LINE       35
 EXPRESSION (((!en_i)) || clr_i)
             ----1----    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       51
 EXPRESSION (set_en_i ? key_i[i] : ({EntropyCopies {entropy_i[i]}}))
             ----1---

-1-	Status	Tests
0	Covered	T12,T13,T44
1	Covered	T1,T3,T16

---

Branch Coverage for Module : keymgr_sideload_key

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	33	4	4	100.00
IF	43	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_sideload_key.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_sideload_key.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	33	if ((!rst_ni))
-2-:	35	if (((!en_i) || clr_i))
-3-:	37	if (set_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	43	if ((!rst_ni))
-2-:	45	if (clr_i)
-3-:	49	if (set_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sideload_ctrl.u_aes_key

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
ALWAYS	33	6	6	100.00
ALWAYS	43	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_sideload_key.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_sideload_key.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	1	1
30	1	1
33	1	1
34	1	1
35	1	1
36	1	1
37	1	1
38	1	1
			MISSING_ELSE
43	1	1
44	1	1
45	1	1
46	1	1
47	1	1
49	1	1
50	1	1
51	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sideload_ctrl.u_aes_key

	Total	Covered	Percent
Conditions	8	7	87.50
Logical	8	7	87.50
Non-Logical	0	0
Event	0	0

 LINE       29
 EXPRESSION (valid_q & en_i)
             ---1---   --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T34

 LINE       35
 EXPRESSION (((!en_i)) || clr_i)
             ----1----    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       51
 EXPRESSION (set_en_i ? key_i[i] : ({EntropyCopies {entropy_i[i]}}))
             ----1---

-1-	Status	Tests
0	Covered	T14
1	Covered	T4,T5,T34

---

Branch Coverage for Instance : tb.dut.u_sideload_ctrl.u_aes_key

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	33	4	4	100.00
IF	43	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_sideload_key.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_sideload_key.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	33	if ((!rst_ni))
-2-:	35	if (((!en_i) || clr_i))
-3-:	37	if (set_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T4,T5,T34
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	43	if ((!rst_ni))
-2-:	45	if (clr_i)
-3-:	49	if (set_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T4,T5,T34
0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sideload_ctrl.u_otbn_key

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
ALWAYS	33	6	6	100.00
ALWAYS	43	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_sideload_key.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_sideload_key.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	1	1
30	1	1
33	1	1
34	1	1
35	1	1
36	1	1
37	1	1
38	1	1
			MISSING_ELSE
43	1	1
44	1	1
45	1	1
46	1	1
47	1	1
49	1	1
50	1	1
51	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sideload_ctrl.u_otbn_key

	Total	Covered	Percent
Conditions	8	7	87.50
Logical	8	7	87.50
Non-Logical	0	0
Event	0	0

 LINE       29
 EXPRESSION (valid_q & en_i)
             ---1---   --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T16

 LINE       35
 EXPRESSION (((!en_i)) || clr_i)
             ----1----    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       51
 EXPRESSION (set_en_i ? key_i[i] : ({EntropyCopies {entropy_i[i]}}))
             ----1---

-1-	Status	Tests
0	Covered	T12,T13,T44
1	Covered	T1,T3,T16

---

Branch Coverage for Instance : tb.dut.u_sideload_ctrl.u_otbn_key

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	33	4	4	100.00
IF	43	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_sideload_key.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_sideload_key.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	33	if ((!rst_ni))
-2-:	35	if (((!en_i) || clr_i))
-3-:	37	if (set_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T16
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	43	if ((!rst_ni))
-2-:	45	if (clr_i)
-3-:	49	if (set_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T16
0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sideload_ctrl.u_kmac_key

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
ALWAYS	33	6	6	100.00
ALWAYS	43	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_sideload_key.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_sideload_key.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	1	1
30	1	1
33	1	1
34	1	1
35	1	1
36	1	1
37	1	1
38	1	1
			MISSING_ELSE
43	1	1
44	1	1
45	1	1
46	1	1
47	1	1
49	1	1
50	1	1
51	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sideload_ctrl.u_kmac_key

	Total	Covered	Percent
Conditions	8	7	87.50
Logical	8	7	87.50
Non-Logical	0	0
Event	0	0

 LINE       29
 EXPRESSION (valid_q & en_i)
             ---1---   --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T17

 LINE       35
 EXPRESSION (((!en_i)) || clr_i)
             ----1----    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       51
 EXPRESSION (set_en_i ? key_i[i] : ({EntropyCopies {entropy_i[i]}}))
             ----1---

-1-	Status	Tests
0	Covered	T14,T43
1	Covered	T2,T4,T17

---

Branch Coverage for Instance : tb.dut.u_sideload_ctrl.u_kmac_key

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	33	4	4	100.00
IF	43	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_sideload_key.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_sideload_key.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	33	if ((!rst_ni))
-2-:	35	if (((!en_i) || clr_i))
-3-:	37	if (set_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T4,T17
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	43	if ((!rst_ni))
-2-:	45	if (clr_i)
-3-:	49	if (set_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T4,T17
0	0	0	Covered	T1,T2,T3