Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3204725	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

621456

1

T1

329

T2

383

T3

619

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3426227	1			T1	356		T2	526		T3	26774
values[0x0]	198509	1			T1	147		T2	111		T3	236
values[0x1]	201445	1			T1	141		T2	125		T3	230

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2197909	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1628272

1

T1

388

T2

458

T3

9469

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12625	1			T2	3		T4	25		T12	11
valid_sources[0x01]	13209	1			T2	3		T4	246		T12	5
valid_sources[0x02]	15236	1			T2	3		T4	15		T12	8
valid_sources[0x03]	12596	1			T2	1		T3	26		T4	21
valid_sources[0x04]	14292	1			T2	4		T3	1		T12	10
valid_sources[0x05]	12884	1			T2	4		T3	27		T4	123
valid_sources[0x06]	13809	1			T3	6		T4	59		T12	6
valid_sources[0x07]	11881	1			T2	1		T3	2		T4	117
valid_sources[0x08]	12330	1			T2	2		T3	23		T4	2
valid_sources[0x09]	12951	1			T2	3		T3	8		T12	4
valid_sources[0x0a]	12217	1			T2	2		T3	4		T4	15
valid_sources[0x0b]	12325	1			T2	4		T4	2		T12	4
valid_sources[0x0c]	13553	1			T2	2		T3	5		T4	72
valid_sources[0x0d]	12654	1			T2	4		T3	2		T12	2
valid_sources[0x0e]	13421	1			T1	644		T2	4		T4	2
valid_sources[0x0f]	13768	1			T2	4		T4	107		T12	6
valid_sources[0x10]	14880	1			T3	22		T4	11		T11	342
valid_sources[0x11]	14145	1			T2	2		T3	2		T4	101
valid_sources[0x12]	17431	1			T2	5		T3	4		T12	5
valid_sources[0x13]	13559	1			T2	5		T3	19		T4	7
valid_sources[0x14]	20521	1			T2	2		T3	1		T4	8
valid_sources[0x15]	14342	1			T2	3		T3	1		T4	96
valid_sources[0x16]	12572	1			T2	2		T3	11		T4	4
valid_sources[0x17]	14022	1			T2	3		T4	68		T12	5
valid_sources[0x18]	13815	1			T2	2		T4	2		T12	5
valid_sources[0x19]	12118	1			T2	2		T3	1		T4	26
valid_sources[0x1a]	12119	1			T3	2		T4	5		T12	3
valid_sources[0x1b]	12776	1			T2	3		T3	5		T4	5
valid_sources[0x1c]	14862	1			T2	2		T4	60		T11	562
valid_sources[0x1d]	24741	1			T2	5		T4	1		T12	5
valid_sources[0x1e]	12035	1			T2	3		T3	6		T12	2
valid_sources[0x1f]	12108	1			T2	2		T4	91		T12	5
valid_sources[0x20]	11819	1			T4	2		T12	1		T14	36
valid_sources[0x21]	12541	1			T2	6		T3	1		T4	46
valid_sources[0x22]	13134	1			T2	3		T3	4		T4	106
valid_sources[0x23]	19031	1			T2	4		T3	15		T4	9
valid_sources[0x24]	12952	1			T2	5		T4	60		T12	6
valid_sources[0x25]	14726	1			T2	4		T4	1		T12	7
valid_sources[0x26]	13479	1			T2	2		T3	7		T4	144
valid_sources[0x27]	12357	1			T2	5		T3	4		T4	27
valid_sources[0x28]	12413	1			T2	1		T4	2		T12	4
valid_sources[0x29]	12912	1			T2	1		T3	35		T4	2
valid_sources[0x2a]	12162	1			T2	1		T3	38		T4	79
valid_sources[0x2b]	12950	1			T2	1		T3	734		T4	2
valid_sources[0x2c]	13573	1			T2	2		T3	4		T4	98
valid_sources[0x2d]	15674	1			T2	6		T3	2		T4	2
valid_sources[0x2e]	12248	1			T3	26		T4	33		T12	4
valid_sources[0x2f]	12623	1			T2	2		T3	161		T4	94
valid_sources[0x30]	13844	1			T2	4		T3	8		T4	16
valid_sources[0x31]	12401	1			T2	2		T4	105		T12	6
valid_sources[0x32]	20146	1			T2	3		T4	5		T12	7
valid_sources[0x33]	16613	1			T2	2		T3	11		T4	18
valid_sources[0x34]	13188	1			T2	1		T4	61		T12	5
valid_sources[0x35]	15895	1			T2	5		T12	5		T14	51
valid_sources[0x36]	14756	1			T2	2		T3	1		T12	2
valid_sources[0x37]	13093	1			T2	4		T3	1		T4	97
valid_sources[0x38]	14036	1			T2	1		T3	49		T12	6
valid_sources[0x39]	11807	1			T2	4		T4	102		T12	3
valid_sources[0x3a]	11834	1			T2	2		T3	580		T4	2
valid_sources[0x3b]	12845	1			T2	1		T4	126		T12	7
valid_sources[0x3c]	17748	1			T2	2		T3	12		T4	129
valid_sources[0x3d]	14001	1			T2	3		T3	1		T4	89
valid_sources[0x3e]	18529	1			T2	4		T4	19		T12	5
valid_sources[0x3f]	12397	1			T2	1		T3	1		T4	101
valid_sources[0x40]	15038	1			T2	1		T4	38		T12	5
valid_sources[0x41]	12811	1			T2	5		T12	5		T14	37
valid_sources[0x42]	12730	1			T2	3		T4	147		T12	4
valid_sources[0x43]	18225	1			T2	6		T3	31		T4	202
valid_sources[0x44]	14619	1			T2	6		T3	2164		T4	1
valid_sources[0x45]	12845	1			T2	4		T3	27		T4	22
valid_sources[0x46]	13443	1			T2	2		T12	7		T14	42
valid_sources[0x47]	13455	1			T2	4		T3	4		T4	134
valid_sources[0x48]	18078	1			T2	2		T3	4		T4	6
valid_sources[0x49]	16072	1			T2	5		T3	3		T4	42
valid_sources[0x4a]	12856	1			T2	7		T3	141		T4	2
valid_sources[0x4b]	14483	1			T2	1		T3	4		T4	145
valid_sources[0x4c]	50839	1			T2	2		T4	238		T12	7
valid_sources[0x4d]	13682	1			T2	3		T3	3		T4	45
valid_sources[0x4e]	12221	1			T2	4		T3	3		T4	31
valid_sources[0x4f]	21685	1			T2	5		T3	18		T4	3
valid_sources[0x50]	12782	1			T2	6		T4	3		T12	5
valid_sources[0x51]	12599	1			T2	3		T3	5		T4	69
valid_sources[0x52]	14117	1			T2	4		T3	2239		T4	2
valid_sources[0x53]	12306	1			T2	5		T3	28		T12	4
valid_sources[0x54]	12424	1			T2	6		T3	1		T4	48
valid_sources[0x55]	12332	1			T2	3		T4	79		T12	4
valid_sources[0x56]	12674	1			T2	1		T4	113		T12	4
valid_sources[0x57]	12271	1			T2	4		T3	5		T4	35
valid_sources[0x58]	12142	1			T2	5		T3	2		T4	100
valid_sources[0x59]	11791	1			T2	1		T3	5		T4	5
valid_sources[0x5a]	30450	1			T2	5		T3	1		T4	148
valid_sources[0x5b]	14024	1			T2	3		T3	2		T4	2
valid_sources[0x5c]	12022	1			T2	2		T4	25		T12	4
valid_sources[0x5d]	16454	1			T2	3		T4	4		T12	12
valid_sources[0x5e]	17509	1			T2	3		T3	552		T4	223
valid_sources[0x5f]	15050	1			T2	3		T3	13		T4	53
valid_sources[0x60]	11788	1			T2	3		T3	25		T4	12
valid_sources[0x61]	13388	1			T2	3		T3	4		T12	5
valid_sources[0x62]	12553	1			T2	3		T4	146		T12	3
valid_sources[0x63]	12677	1			T2	3		T3	37		T4	43
valid_sources[0x64]	11853	1			T3	1		T4	99		T12	9
valid_sources[0x65]	13108	1			T2	3		T3	650		T4	50
valid_sources[0x66]	42231	1			T2	3		T3	6		T4	166
valid_sources[0x67]	11850	1			T2	2		T4	266		T12	9
valid_sources[0x68]	13071	1			T2	1		T3	9		T4	189
valid_sources[0x69]	13892	1			T2	6		T3	4		T4	102
valid_sources[0x6a]	12997	1			T2	6		T3	28		T4	32
valid_sources[0x6b]	12807	1			T2	4		T4	89		T12	3
valid_sources[0x6c]	15174	1			T2	4		T3	1993		T4	171
valid_sources[0x6d]	11492	1			T2	3		T4	35		T12	6
valid_sources[0x6e]	12305	1			T2	2		T3	8		T4	181
valid_sources[0x6f]	12586	1			T4	68		T12	7		T14	50
valid_sources[0x70]	13489	1			T2	5		T3	4		T4	22
valid_sources[0x71]	15310	1			T2	5		T3	905		T4	4
valid_sources[0x72]	26094	1			T2	1		T4	196		T12	3
valid_sources[0x73]	12409	1			T2	5		T3	11		T4	74
valid_sources[0x74]	13836	1			T2	3		T3	29		T4	71
valid_sources[0x75]	12240	1			T4	107		T12	2		T14	37
valid_sources[0x76]	13875	1			T2	1		T4	52		T12	3
valid_sources[0x77]	31071	1			T2	2		T4	39		T12	6
valid_sources[0x78]	12079	1			T2	3		T4	54		T12	3
valid_sources[0x79]	12892	1			T2	6		T3	18		T4	19
valid_sources[0x7a]	12714	1			T2	3		T3	44		T4	168
valid_sources[0x7b]	12606	1			T2	2		T4	154		T12	4
valid_sources[0x7c]	13488	1			T2	3		T4	7		T12	4
valid_sources[0x7d]	13575	1			T2	1		T4	96		T12	12
valid_sources[0x7e]	11709	1			T2	2		T4	107		T12	8
valid_sources[0x7f]	20471	1			T2	3		T4	218		T12	8
valid_sources[0x80]	13976	1			T2	1		T4	2		T12	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

350808

1

T1

137

T2

237

T3

303

values[0x0]

all_enables

biggest_size

142659

1

T1

107

T2

74

T3

165

values[0x1]

all_enables

biggest_size

127989

1

T1

85

T2

72

T3

151