Unified Coverage Report :: Module :: keymgr_kmac_if

Module : keymgr_kmac_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.66	100.00	90.91		54.55	92.86	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_kmac_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_kmac_if	96.75	100.00	90.91		100.00	92.86	100.00

---

Module Instance : tb.dut.u_kmac_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.75	100.00	90.91		100.00	92.86	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.35	100.00	90.91	100.00	100.00	93.18	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.94	96.00	97.81	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_cnt	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : keymgr_kmac_if

	Line No.	Total	Covered	Percent
TOTAL		112	112	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	135	1	1	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
ALWAYS	161	3	3	100.00
ALWAYS	169	3	3	100.00
ALWAYS	172	56	56	100.00
CONT_ASSIGN	287	1	1	100.00
ALWAYS	296	8	8	100.00
CONT_ASSIGN	313	1	1	100.00
CONT_ASSIGN	318	1	1	100.00
CONT_ASSIGN	319	1	1	100.00
CONT_ASSIGN	322	1	1	100.00
CONT_ASSIGN	323	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
ALWAYS	330	9	9	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	343	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	351	1	1	100.00
CONT_ASSIGN	356	1	1	100.00
CONT_ASSIGN	357	1	1	100.00
ALWAYS	363	4	4	100.00
CONT_ASSIGN	369	1	1	100.00
CONT_ASSIGN	375	1	1	100.00
ALWAYS	379	7	7	100.00
CONT_ASSIGN	391	1	1	100.00
CONT_ASSIGN	394	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_kmac_if.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_kmac_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
134	1	1
135	1	1
136	1	1
138	1	1
161	1	1
162	1	1
164	1	1
169	3	3
172	1	1
173	1	1
174	1	1
175	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
182	1	1
183	1	1
184	1	1
186	1	1
188	1	1
190	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
204	1	1
205	1	1
			==> MISSING_ELSE
208	1	1
			MISSING_ELSE
213	1	1
214	1	1
217	1	1
218	1	1
221	1	1
222	1	1
			MISSING_ELSE
			MISSING_ELSE
229	1	1
230	1	1
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
241	1	1
242	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
256	1	1
257	1	1
260	1	1
261	1	1
262	1	1
263	1	1
			==> MISSING_ELSE
279	1	1
280	1	1
281	1	1
282	1	1
			MISSING_ELSE
287	1	1
296	1	1
298	1	1
299	1	1
300	1	1
301	1	1
303	1	1
305	1	1
307	1	1
			MISSING_ELSE
313	1	1
318	1	1
319	1	1
322	1	1
323	1	1
324	1	1
330	1	1
331	1	1
332	1	1
333	1	1
334	1	1
335	1	1
336	1	1
337	1	1
338	1	1
			MISSING_ELSE
342	1	1
343	1	1
344	1	1
349	1	1
351	1	1
356	1	1
357	1	1
363	1	1
364	1	1
365	1	1
366	1	1
			MISSING_ELSE
369	1	1
375	1	1
379	1	1
380	1	1
381	1	1
382	1	1
384	1	1
385	1	1
386	1	1
391	1	1
394	1	1

---

Cond Coverage for Module : keymgr_kmac_if

	Total	Covered	Percent
Conditions	77	70	90.91
Logical	77	70	90.91
Non-Logical	0	0
Event	0	0

 LINE       138
 EXPRESSION (adv_en_i | id_en_i | gen_en_i)
             ----1---   ---2---   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	1	0	Covered	T2,T3,T4
1	0	0	Covered	T2,T3,T4

 LINE       208
 EXPRESSION ((rounds == 5'b0) ? StTxLast : StTx)
             --------1-------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Not Covered

 LINE       208
 SUB-EXPRESSION (rounds == 5'b0)
                --------1-------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Not Covered

 LINE       221
 EXPRESSION (cnt == 5'(1'b1))
            --------1--------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       242
 EXPRESSION (kmac_data_i.ready ? StOpWait : StTxLast)
             --------1--------

-1-	Status	Tests
0	Covered	T3,T12,T13
1	Covered	T2,T3,T4

 LINE       287
 EXPRESSION 
 Number  Term
      1  (start && done_o) ? ({kmac_data_i.digest_share1, kmac_data_i.digest_share0}) : ({{DecoyOutputCopies {entropy_i[1]}}, {DecoyOutputCopies {entropy_i[0]}}}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       287
 SUB-EXPRESSION (start && done_o)
                 --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T17,T9
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       301
 EXPRESSION (adv_en_i & (inputs_invalid_i[OpAdvance] | inputs_invalid_q[OpAdvance]))
             ----1---   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T18
1	0	Covered	T2,T3,T4
1	1	Covered	T19,T20,T21

 LINE       301
 SUB-EXPRESSION (inputs_invalid_i[OpAdvance] | inputs_invalid_q[OpAdvance])
                 -------------1-------------   -------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Not Covered
1	0	Covered	T19,T20,T21

 LINE       303
 EXPRESSION (id_en_i & (inputs_invalid_i[OpGenId] | inputs_invalid_q[OpGenId]))
             ---1---   ---------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T18
1	0	Covered	T2,T3,T4
1	1	Not Covered

 LINE       303
 SUB-EXPRESSION (inputs_invalid_i[OpGenId] | inputs_invalid_q[OpGenId])
                 ------------1------------   ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Not Covered
1	0	Covered	T18

 LINE       305
 EXPRESSION (gen_en_i & (inputs_invalid_i[OpGenSwOut] | inputs_invalid_q[OpGenSwOut]))
             ----1---   ------------------------------2------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T4,T22,T5

 LINE       305
 SUB-EXPRESSION (inputs_invalid_i[OpGenSwOut] | inputs_invalid_q[OpGenSwOut])
                 --------------1-------------   --------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Not Covered
1	0	Covered	T2,T3,T4

 LINE       307
 EXPRESSION (gen_en_i & (inputs_invalid_i[OpGenHwOut] | inputs_invalid_q[OpGenHwOut]))
             ----1---   ------------------------------2------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T4,T22,T5

 LINE       307
 SUB-EXPRESSION (inputs_invalid_i[OpGenHwOut] | inputs_invalid_q[OpGenHwOut])
                 --------------1-------------   --------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Not Covered
1	0	Covered	T2,T3,T4

 LINE       331
 EXPRESSION (((|cmd_error_o)) || inputs_invalid_o || fsm_error_o)
             --------1-------    --------2-------    -----3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T8,T9,T10
0	1	0	Covered	T4,T22,T5
1	0	0	Covered	T13,T17,T23

 LINE       333
 EXPRESSION (valid && adv_en_i)
             --1--    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       335
 EXPRESSION (valid && id_en_i)
             --1--    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       337
 EXPRESSION (valid && gen_en_i)
             --1--    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T24,T25,T26
1	1	Covered	T2,T3,T4

 LINE       349
 EXPRESSION ((((~kmac_done_vld)) & kmac_data_i.done) | kmac_done_err_q)
             -------------------1-------------------   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T27,T28,T29
1	0	Covered	T2,T3,T4

 LINE       349
 SUB-EXPRESSION (((~kmac_done_vld)) & kmac_data_i.done)
                 ---------1--------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       369
 EXPRESSION ((cmd_chk & (enables_q != enables_d)) | cmd_consty_err_q)
             ------------------1-----------------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T17,T23
1	0	Covered	T13,T17,T23

 LINE       369
 SUB-EXPRESSION (cmd_chk & (enables_q != enables_d))
                 ---1---   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T13,T17,T23

 LINE       369
 SUB-EXPRESSION (enables_q != enables_d)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       375
 EXPRESSION (((|(enables_d & enables_sub))) | one_hot_err_q)
             ---------------1--------------   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T17,T23
1	0	Covered	T13,T17,T23

 LINE       391
 EXPRESSION (one_hot_err_q | cmd_consty_err_q)
             ------1------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T24,T25,T26
1	0	Covered	T17,T23,T18

 LINE       394
 EXPRESSION (kmac_data_o.valid & kmac_data_i.ready)
             --------1--------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T12,T13
1	1	Covered	T2,T3,T4

---

FSM Coverage for Module : keymgr_kmac_if

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	11	6	54.55
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StClean	251	Covered	T2,T3,T4
StError	280	Covered	T8,T9,T10
StIdle	263	Covered	T1,T2,T3
StOpWait	242	Covered	T2,T3,T4
StTx	208	Covered	T2,T3,T4
StTxLast	208	Covered	T2,T3,T4

transitions	Line No.	Covered	Tests
StClean->StError	280	Not Covered
StClean->StIdle	263	Covered	T2,T3,T4
StIdle->StError	280	Covered	T8,T9,T10
StIdle->StTx	208	Covered	T2,T3,T4
StIdle->StTxLast	208	Not Covered
StOpWait->StClean	251	Covered	T2,T3,T4
StOpWait->StError	280	Not Covered
StTx->StError	280	Not Covered
StTx->StTxLast	222	Covered	T2,T3,T4
StTxLast->StError	280	Not Covered
StTxLast->StOpWait	242	Covered	T2,T3,T4

---

Branch Coverage for Module : keymgr_kmac_if

	Line No.	Total	Covered	Percent
Branches		42	39	92.86
TERNARY	287	2	2	100.00
IF	161	2	2	100.00
IF	169	2	2	100.00
CASE	190	21	18	85.71
IF	279	2	2	100.00
IF	298	3	3	100.00
IF	331	5	5	100.00
IF	363	3	3	100.00
IF	379	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_kmac_if.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_kmac_if.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	287	((start && done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	161	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	169	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	190	case (state_q)
-2-:	198	if (start)
-3-:	200	if (adv_en_i)
-4-:	202	if (id_en_i)
-5-:	204	if (gen_en_i)
-6-:	208	((rounds == 5'b0)) ? 
-7-:	217	if (kmac_data_i.ready)
-8-:	221	if ((cnt == 5'(1'b1)))
-9-:	232	if (adv_en_i)
-10-:	234	if (id_en_i)
-11-:	236	if (gen_en_i)
-12-:	242	(kmac_data_i.ready) ? 
-13-:	248	if (kmac_data_i.done)
-14-:	260	if ((!start))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
StIdle	1	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
StIdle	1	0	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
StIdle	1	0	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
StIdle	1	0	0	0	-	-	-	-	-	-	-	-	-	Not Covered
StIdle	1	-	-	-	1	-	-	-	-	-	-	-	-	Not Covered
StIdle	1	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
StIdle	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StTx	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T4
StTx	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T2,T3,T4
StTx	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T3,T12,T13
StTxLast	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T2,T3,T4
StTxLast	-	-	-	-	-	-	-	0	1	-	-	-	-	Covered	T2,T3,T4
StTxLast	-	-	-	-	-	-	-	0	0	1	-	-	-	Covered	T2,T3,T4
StTxLast	-	-	-	-	-	-	-	0	0	0	-	-	-	Covered	T17,T23,T24
StTxLast	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T2,T3,T4
StTxLast	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T3,T12,T13
StOpWait	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T3,T4
StOpWait	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T2,T3,T4
StClean	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T3,T4
StClean	-	-	-	-	-	-	-	-	-	-	-	-	0	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	279	if (cnt_err)

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	298	if (clr_err)
-2-:	300	if (valid)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	331	if ((((|cmd_error_o) || inputs_invalid_o) || fsm_error_o))
-2-:	333	if ((valid && adv_en_i))
-3-:	335	if ((valid && id_en_i))
-4-:	337	if ((valid && gen_en_i))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T4,T13,T22
0	1	-	-	Covered	T2,T3,T4
0	0	1	-	Covered	T2,T3,T4
0	0	0	1	Covered	T2,T3,T4
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	363	if ((!rst_ni))
-2-:	365	if (cnt_set)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	379	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : keymgr_kmac_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AdvRemBytes_A	879	879	0	0
GenRemBytes_A	879	879	0	0
IdRemBytes_A	879	879	0	0
LastStrb_A	21177221	14008431	0	0
u_state_regs_A	21697481	21532780	0	0

AdvRemBytes_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	879	879	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

GenRemBytes_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	879	879	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

IdRemBytes_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	879	879	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

LastStrb_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21177221	14008431	0	0
T2	9935	271	0	0
T3	56554	52598	0	0
T4	55937	4444	0	0
T5	0	150379	0	0
T11	16566	546	0	0
T12	14448	3664	0	0
T13	7312	2831	0	0
T14	23320	18107	0	0
T15	114013	111593	0	0
T16	1103	0	0	0
T22	23163	14180	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21697481	21532780	0	0
T1	2752	2688	0	0
T2	9935	9852	0	0
T3	56554	56463	0	0
T4	55937	54612	0	0
T11	16566	16460	0	0
T12	14448	14379	0	0
T13	12143	12038	0	0
T14	23320	23267	0	0
T15	114013	113957	0	0
T16	1103	1034	0	0

Line Coverage for Instance : tb.dut.u_kmac_if

	Line No.	Total	Covered	Percent
TOTAL		112	112	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	135	1	1	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
ALWAYS	161	3	3	100.00
ALWAYS	169	3	3	100.00
ALWAYS	172	56	56	100.00
CONT_ASSIGN	287	1	1	100.00
ALWAYS	296	8	8	100.00
CONT_ASSIGN	313	1	1	100.00
CONT_ASSIGN	318	1	1	100.00
CONT_ASSIGN	319	1	1	100.00
CONT_ASSIGN	322	1	1	100.00
CONT_ASSIGN	323	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
ALWAYS	330	9	9	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	343	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	351	1	1	100.00
CONT_ASSIGN	356	1	1	100.00
CONT_ASSIGN	357	1	1	100.00
ALWAYS	363	4	4	100.00
CONT_ASSIGN	369	1	1	100.00
CONT_ASSIGN	375	1	1	100.00
ALWAYS	379	7	7	100.00
CONT_ASSIGN	391	1	1	100.00
CONT_ASSIGN	394	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_kmac_if.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_kmac_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
134	1	1
135	1	1
136	1	1
138	1	1
161	1	1
162	1	1
164	1	1
169	3	3
172	1	1
173	1	1
174	1	1
175	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
182	1	1
183	1	1
184	1	1
186	1	1
188	1	1
190	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
204	1	1
205	1	1
			==> MISSING_ELSE
208	1	1
			MISSING_ELSE
213	1	1
214	1	1
217	1	1
218	1	1
221	1	1
222	1	1
			MISSING_ELSE
			MISSING_ELSE
229	1	1
230	1	1
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
241	1	1
242	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
256	1	1
257	1	1
260	1	1
261	1	1
262	1	1
263	1	1
			==> MISSING_ELSE
279	1	1
280	1	1
281	1	1
282	1	1
			MISSING_ELSE
287	1	1
296	1	1
298	1	1
299	1	1
300	1	1
301	1	1
303	1	1
305	1	1
307	1	1
			MISSING_ELSE
313	1	1
318	1	1
319	1	1
322	1	1
323	1	1
324	1	1
330	1	1
331	1	1
332	1	1
333	1	1
334	1	1
335	1	1
336	1	1
337	1	1
338	1	1
			MISSING_ELSE
342	1	1
343	1	1
344	1	1
349	1	1
351	1	1
356	1	1
357	1	1
363	1	1
364	1	1
365	1	1
366	1	1
			MISSING_ELSE
369	1	1
375	1	1
379	1	1
380	1	1
381	1	1
382	1	1
384	1	1
385	1	1
386	1	1
391	1	1
394	1	1

---

Cond Coverage for Instance : tb.dut.u_kmac_if

	Total	Covered	Percent
Conditions	77	70	90.91
Logical	77	70	90.91
Non-Logical	0	0
Event	0	0

 LINE       138
 EXPRESSION (adv_en_i | id_en_i | gen_en_i)
             ----1---   ---2---   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	1	0	Covered	T2,T3,T4
1	0	0	Covered	T2,T3,T4

 LINE       208
 EXPRESSION ((rounds == 5'b0) ? StTxLast : StTx)
             --------1-------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Not Covered

 LINE       208
 SUB-EXPRESSION (rounds == 5'b0)
                --------1-------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Not Covered

 LINE       221
 EXPRESSION (cnt == 5'(1'b1))
            --------1--------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       242
 EXPRESSION (kmac_data_i.ready ? StOpWait : StTxLast)
             --------1--------

-1-	Status	Tests
0	Covered	T3,T12,T13
1	Covered	T2,T3,T4

 LINE       287
 EXPRESSION 
 Number  Term
      1  (start && done_o) ? ({kmac_data_i.digest_share1, kmac_data_i.digest_share0}) : ({{DecoyOutputCopies {entropy_i[1]}}, {DecoyOutputCopies {entropy_i[0]}}}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       287
 SUB-EXPRESSION (start && done_o)
                 --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T8,T17,T9
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       301
 EXPRESSION (adv_en_i & (inputs_invalid_i[OpAdvance] | inputs_invalid_q[OpAdvance]))
             ----1---   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T18
1	0	Covered	T2,T3,T4
1	1	Covered	T19,T20,T21

 LINE       301
 SUB-EXPRESSION (inputs_invalid_i[OpAdvance] | inputs_invalid_q[OpAdvance])
                 -------------1-------------   -------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Not Covered
1	0	Covered	T19,T20,T21

 LINE       303
 EXPRESSION (id_en_i & (inputs_invalid_i[OpGenId] | inputs_invalid_q[OpGenId]))
             ---1---   ---------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T18
1	0	Covered	T2,T3,T4
1	1	Not Covered

 LINE       303
 SUB-EXPRESSION (inputs_invalid_i[OpGenId] | inputs_invalid_q[OpGenId])
                 ------------1------------   ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Not Covered
1	0	Covered	T18

 LINE       305
 EXPRESSION (gen_en_i & (inputs_invalid_i[OpGenSwOut] | inputs_invalid_q[OpGenSwOut]))
             ----1---   ------------------------------2------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T4,T22,T5

 LINE       305
 SUB-EXPRESSION (inputs_invalid_i[OpGenSwOut] | inputs_invalid_q[OpGenSwOut])
                 --------------1-------------   --------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Not Covered
1	0	Covered	T2,T3,T4

 LINE       307
 EXPRESSION (gen_en_i & (inputs_invalid_i[OpGenHwOut] | inputs_invalid_q[OpGenHwOut]))
             ----1---   ------------------------------2------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T4,T22,T5

 LINE       307
 SUB-EXPRESSION (inputs_invalid_i[OpGenHwOut] | inputs_invalid_q[OpGenHwOut])
                 --------------1-------------   --------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Not Covered
1	0	Covered	T2,T3,T4

 LINE       331
 EXPRESSION (((|cmd_error_o)) || inputs_invalid_o || fsm_error_o)
             --------1-------    --------2-------    -----3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T8,T9,T10
0	1	0	Covered	T4,T22,T5
1	0	0	Covered	T13,T17,T23

 LINE       333
 EXPRESSION (valid && adv_en_i)
             --1--    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       335
 EXPRESSION (valid && id_en_i)
             --1--    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       337
 EXPRESSION (valid && gen_en_i)
             --1--    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T24,T25,T26
1	1	Covered	T2,T3,T4

 LINE       349
 EXPRESSION ((((~kmac_done_vld)) & kmac_data_i.done) | kmac_done_err_q)
             -------------------1-------------------   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T27,T28,T29
1	0	Covered	T2,T3,T4

 LINE       349
 SUB-EXPRESSION (((~kmac_done_vld)) & kmac_data_i.done)
                 ---------1--------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       369
 EXPRESSION ((cmd_chk & (enables_q != enables_d)) | cmd_consty_err_q)
             ------------------1-----------------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T17,T23
1	0	Covered	T13,T17,T23

 LINE       369
 SUB-EXPRESSION (cmd_chk & (enables_q != enables_d))
                 ---1---   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T13,T17,T23

 LINE       369
 SUB-EXPRESSION (enables_q != enables_d)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       375
 EXPRESSION (((|(enables_d & enables_sub))) | one_hot_err_q)
             ---------------1--------------   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T17,T23
1	0	Covered	T13,T17,T23

 LINE       391
 EXPRESSION (one_hot_err_q | cmd_consty_err_q)
             ------1------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T24,T25,T26
1	0	Covered	T17,T23,T18

 LINE       394
 EXPRESSION (kmac_data_o.valid & kmac_data_i.ready)
             --------1--------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T12,T13
1	1	Covered	T2,T3,T4

---

FSM Coverage for Instance : tb.dut.u_kmac_if

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StClean	251	Covered	T2,T3,T4
StError	280	Covered	T8,T9,T10
StIdle	263	Covered	T1,T2,T3
StOpWait	242	Covered	T2,T3,T4
StTx	208	Covered	T2,T3,T4
StTxLast	208	Covered	T2,T3,T4

transitions	Line No.	Covered	Tests
StClean->StError	280	Excluded
StClean->StIdle	263	Covered	T2,T3,T4
StIdle->StError	280	Covered	T8,T9,T10
StIdle->StTx	208	Covered	T2,T3,T4
StIdle->StTxLast	208	Excluded
StOpWait->StClean	251	Covered	T2,T3,T4
StOpWait->StError	280	Excluded
StTx->StError	280	Excluded
StTx->StTxLast	222	Covered	T2,T3,T4
StTxLast->StError	280	Excluded
StTxLast->StOpWait	242	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_kmac_if

	Line No.	Total	Covered	Percent
Branches		42	39	92.86
TERNARY	287	2	2	100.00
IF	161	2	2	100.00
IF	169	2	2	100.00
CASE	190	21	18	85.71
IF	279	2	2	100.00
IF	298	3	3	100.00
IF	331	5	5	100.00
IF	363	3	3	100.00
IF	379	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_kmac_if.sv' or '../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_kmac_if.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	287	((start && done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	161	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	169	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	190	case (state_q)
-2-:	198	if (start)
-3-:	200	if (adv_en_i)
-4-:	202	if (id_en_i)
-5-:	204	if (gen_en_i)
-6-:	208	((rounds == 5'b0)) ? 
-7-:	217	if (kmac_data_i.ready)
-8-:	221	if ((cnt == 5'(1'b1)))
-9-:	232	if (adv_en_i)
-10-:	234	if (id_en_i)
-11-:	236	if (gen_en_i)
-12-:	242	(kmac_data_i.ready) ? 
-13-:	248	if (kmac_data_i.done)
-14-:	260	if ((!start))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
StIdle	1	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
StIdle	1	0	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
StIdle	1	0	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
StIdle	1	0	0	0	-	-	-	-	-	-	-	-	-	Not Covered
StIdle	1	-	-	-	1	-	-	-	-	-	-	-	-	Not Covered
StIdle	1	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
StIdle	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StTx	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T4
StTx	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T2,T3,T4
StTx	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T3,T12,T13
StTxLast	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T2,T3,T4
StTxLast	-	-	-	-	-	-	-	0	1	-	-	-	-	Covered	T2,T3,T4
StTxLast	-	-	-	-	-	-	-	0	0	1	-	-	-	Covered	T2,T3,T4
StTxLast	-	-	-	-	-	-	-	0	0	0	-	-	-	Covered	T17,T23,T24
StTxLast	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T2,T3,T4
StTxLast	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T3,T12,T13
StOpWait	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T3,T4
StOpWait	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T2,T3,T4
StClean	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T3,T4
StClean	-	-	-	-	-	-	-	-	-	-	-	-	0	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	279	if (cnt_err)

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	298	if (clr_err)
-2-:	300	if (valid)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	331	if ((((|cmd_error_o) || inputs_invalid_o) || fsm_error_o))
-2-:	333	if ((valid && adv_en_i))
-3-:	335	if ((valid && id_en_i))
-4-:	337	if ((valid && gen_en_i))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T4,T13,T22
0	1	-	-	Covered	T2,T3,T4
0	0	1	-	Covered	T2,T3,T4
0	0	0	1	Covered	T2,T3,T4
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	363	if ((!rst_ni))
-2-:	365	if (cnt_set)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	379	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_kmac_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AdvRemBytes_A	879	879	0	0
GenRemBytes_A	879	879	0	0
IdRemBytes_A	879	879	0	0
LastStrb_A	21177221	14008431	0	0
u_state_regs_A	21697481	21532780	0	0

AdvRemBytes_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	879	879	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

GenRemBytes_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	879	879	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

IdRemBytes_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	879	879	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

LastStrb_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21177221	14008431	0	0
T2	9935	271	0	0
T3	56554	52598	0	0
T4	55937	4444	0	0
T5	0	150379	0	0
T11	16566	546	0	0
T12	14448	3664	0	0
T13	7312	2831	0	0
T14	23320	18107	0	0
T15	114013	111593	0	0
T16	1103	0	0	0
T22	23163	14180	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21697481	21532780	0	0
T1	2752	2688	0	0
T2	9935	9852	0	0
T3	56554	56463	0	0
T4	55937	54612	0	0
T11	16566	16460	0	0
T12	14448	14379	0	0
T13	12143	12038	0	0
T14	23320	23267	0	0
T15	114013	113957	0	0
T16	1103	1034	0	0