Unified Coverage Report :: Module :: keymgr_csr_assert_fpv

Module : keymgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_csr_assert_0/keymgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.94	96.00	97.81	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	23423716	14118	0	0
attest_sw_binding_0_rd_A	23423716	3052	0	0
attest_sw_binding_1_rd_A	23423716	2867	0	0
attest_sw_binding_2_rd_A	23423716	3108	0	0
attest_sw_binding_3_rd_A	23423716	3215	0	0
attest_sw_binding_4_rd_A	23423716	3103	0	0
attest_sw_binding_5_rd_A	23423716	3013	0	0
attest_sw_binding_6_rd_A	23423716	2960	0	0
attest_sw_binding_7_rd_A	23423716	3008	0	0
intr_enable_rd_A	23423716	3851	0	0
key_version_rd_A	23423716	3089	0	0
max_creator_key_ver_regwen_rd_A	23423716	3132	0	0
max_owner_int_key_ver_regwen_rd_A	23423716	3012	0	0
max_owner_key_ver_regwen_rd_A	23423716	3072	0	0
reseed_interval_regwen_rd_A	23423716	3127	0	0
salt_0_rd_A	23423716	3045	0	0
salt_1_rd_A	23423716	3205	0	0
salt_2_rd_A	23423716	3208	0	0
salt_3_rd_A	23423716	3096	0	0
salt_4_rd_A	23423716	3107	0	0
salt_5_rd_A	23423716	3135	0	0
salt_6_rd_A	23423716	3059	0	0
salt_7_rd_A	23423716	3026	0	0
sealing_sw_binding_0_rd_A	23423716	2794	0	0
sealing_sw_binding_1_rd_A	23423716	3061	0	0
sealing_sw_binding_2_rd_A	23423716	2994	0	0
sealing_sw_binding_3_rd_A	23423716	2968	0	0
sealing_sw_binding_4_rd_A	23423716	2936	0	0
sealing_sw_binding_5_rd_A	23423716	3197	0	0
sealing_sw_binding_6_rd_A	23423716	3105	0	0
sealing_sw_binding_7_rd_A	23423716	3065	0	0
sideload_clear_rd_A	23423716	3063	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23423716	14118	0	0
T5	282651	0	0	0
T11	16566	26	0	0
T12	14448	0	0	0
T13	12143	0	0	0
T14	23320	0	0	0
T15	114013	0	0	0
T16	1103	0	0	0
T22	23163	0	0	0
T30	9197	0	0	0
T56	19839	845	0	0
T57	0	214	0	0
T74	0	213	0	0
T75	0	393	0	0
T76	0	373	0	0
T78	0	345	0	0
T79	0	241	0	0
T80	0	765	0	0
T81	0	24	0	0

attest_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23423716	3052	0	0
T6	408916	0	0	0
T43	3750	0	0	0
T66	0	143	0	0
T67	0	170	0	0
T74	45372	38	0	0
T94	0	14	0	0
T95	0	64	0	0
T121	62145	0	0	0
T165	0	37	0	0
T166	0	29	0	0
T167	0	8	0	0
T168	0	7	0	0
T169	0	243	0	0
T170	2890	0	0	0
T171	9041	0	0	0
T172	4484	0	0	0
T173	19071	0	0	0
T174	7465	0	0	0
T175	9470	0	0	0

attest_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23423716	2867	0	0
T6	408916	0	0	0
T43	3750	0	0	0
T66	0	112	0	0
T67	0	189	0	0
T74	45372	39	0	0
T94	0	6	0	0
T95	0	21	0	0
T121	62145	0	0	0
T165	0	43	0	0
T166	0	36	0	0
T167	0	22	0	0
T168	0	1	0	0
T169	0	232	0	0
T170	2890	0	0	0
T171	9041	0	0	0
T172	4484	0	0	0
T173	19071	0	0	0
T174	7465	0	0	0
T175	9470	0	0	0

attest_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23423716	3108	0	0
T6	408916	0	0	0
T43	3750	0	0	0
T66	0	101	0	0
T67	0	210	0	0
T74	45372	30	0	0
T95	0	69	0	0
T121	62145	0	0	0
T165	0	34	0	0
T166	0	32	0	0
T167	0	35	0	0
T168	0	1	0	0
T169	0	213	0	0
T170	2890	0	0	0
T171	9041	0	0	0
T172	4484	0	0	0
T173	19071	0	0	0
T174	7465	0	0	0
T175	9470	0	0	0
T176	0	138	0	0

attest_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23423716	3215	0	0
T6	408916	0	0	0
T43	3750	0	0	0
T66	0	117	0	0
T67	0	196	0	0
T74	45372	25	0	0
T94	0	7	0	0
T95	0	79	0	0
T121	62145	0	0	0
T165	0	30	0	0
T166	0	31	0	0
T167	0	10	0	0
T168	0	7	0	0
T169	0	263	0	0
T170	2890	0	0	0
T171	9041	0	0	0
T172	4484	0	0	0
T173	19071	0	0	0
T174	7465	0	0	0
T175	9470	0	0	0

attest_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23423716	3103	0	0
T6	408916	0	0	0
T43	3750	0	0	0
T66	0	128	0	0
T67	0	204	0	0
T74	45372	49	0	0
T94	0	2	0	0
T95	0	21	0	0
T121	62145	0	0	0
T165	0	17	0	0
T166	0	21	0	0
T167	0	26	0	0
T168	0	5	0	0
T169	0	256	0	0
T170	2890	0	0	0
T171	9041	0	0	0
T172	4484	0	0	0
T173	19071	0	0	0
T174	7465	0	0	0
T175	9470	0	0	0

attest_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23423716	3013	0	0
T6	408916	0	0	0
T43	3750	0	0	0
T66	0	99	0	0
T67	0	191	0	0
T74	45372	43	0	0
T95	0	30	0	0
T121	62145	0	0	0
T165	0	50	0	0
T166	0	46	0	0
T167	0	19	0	0
T168	0	6	0	0
T169	0	230	0	0
T170	2890	0	0	0
T171	9041	0	0	0
T172	4484	0	0	0
T173	19071	0	0	0
T174	7465	0	0	0
T175	9470	0	0	0
T176	0	111	0	0

attest_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23423716	2960	0	0
T6	408916	0	0	0
T43	3750	0	0	0
T66	0	101	0	0
T67	0	195	0	0
T74	45372	29	0	0
T94	0	9	0	0
T95	0	77	0	0
T121	62145	0	0	0
T165	0	30	0	0
T166	0	19	0	0
T167	0	13	0	0
T168	0	3	0	0
T169	0	229	0	0
T170	2890	0	0	0
T171	9041	0	0	0
T172	4484	0	0	0
T173	19071	0	0	0
T174	7465	0	0	0
T175	9470	0	0	0

attest_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23423716	3008	0	0
T6	408916	0	0	0
T43	3750	0	0	0
T66	0	90	0	0
T67	0	216	0	0
T74	45372	30	0	0
T95	0	36	0	0
T121	62145	0	0	0
T156	0	54	0	0
T165	0	36	0	0
T166	0	51	0	0
T167	0	39	0	0
T169	0	263	0	0
T170	2890	0	0	0
T171	9041	0	0	0
T172	4484	0	0	0
T173	19071	0	0	0
T174	7465	0	0	0
T175	9470	0	0	0
T176	0	109	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23423716	3851	0	0
T6	408916	0	0	0
T43	3750	0	0	0
T74	45372	55	0	0
T110	0	23	0	0
T121	62145	0	0	0
T132	0	51	0	0
T165	0	53	0	0
T166	0	97	0	0
T170	2890	0	0	0
T171	9041	0	0	0
T172	4484	0	0	0
T173	19071	0	0	0
T174	7465	0	0	0
T175	9470	0	0	0
T177	0	7	0	0
T178	0	57	0	0
T179	0	65	0	0
T180	0	79	0	0
T181	0	52	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23423716	3089	0	0
T6	408916	0	0	0
T43	3750	0	0	0
T66	0	106	0	0
T67	0	234	0	0
T74	45372	17	0	0
T95	0	40	0	0
T121	62145	0	0	0
T165	0	35	0	0
T166	0	42	0	0
T167	0	18	0	0
T168	0	4	0	0
T169	0	230	0	0
T170	2890	0	0	0
T171	9041	0	0	0
T172	4484	0	0	0
T173	19071	0	0	0
T174	7465	0	0	0
T175	9470	0	0	0
T176	0	137	0	0

max_creator_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23423716	3132	0	0
T6	408916	0	0	0
T43	3750	0	0	0
T66	0	117	0	0
T67	0	188	0	0
T74	45372	44	0	0
T94	0	3	0	0
T95	0	69	0	0
T121	62145	0	0	0
T165	0	48	0	0
T166	0	67	0	0
T167	0	31	0	0
T168	0	3	0	0
T169	0	241	0	0
T170	2890	0	0	0
T171	9041	0	0	0
T172	4484	0	0	0
T173	19071	0	0	0
T174	7465	0	0	0
T175	9470	0	0	0

max_owner_int_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23423716	3012	0	0
T6	408916	0	0	0
T43	3750	0	0	0
T66	0	87	0	0
T67	0	207	0	0
T74	45372	35	0	0
T94	0	7	0	0
T95	0	16	0	0
T121	62145	0	0	0
T165	0	31	0	0
T166	0	36	0	0
T167	0	12	0	0
T168	0	2	0	0
T169	0	261	0	0
T170	2890	0	0	0
T171	9041	0	0	0
T172	4484	0	0	0
T173	19071	0	0	0
T174	7465	0	0	0
T175	9470	0	0	0

max_owner_key_ver_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23423716	3072	0	0
T6	408916	0	0	0
T43	3750	0	0	0
T66	0	105	0	0
T67	0	207	0	0
T74	45372	23	0	0
T94	0	5	0	0
T95	0	47	0	0
T121	62145	0	0	0
T165	0	38	0	0
T166	0	20	0	0
T167	0	8	0	0
T168	0	6	0	0
T169	0	229	0	0
T170	2890	0	0	0
T171	9041	0	0	0
T172	4484	0	0	0
T173	19071	0	0	0
T174	7465	0	0	0
T175	9470	0	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23423716	3127	0	0
T6	408916	0	0	0
T43	3750	0	0	0
T66	0	94	0	0
T67	0	193	0	0
T74	45372	23	0	0
T94	0	10	0	0
T95	0	42	0	0
T121	62145	0	0	0
T165	0	23	0	0
T166	0	32	0	0
T167	0	31	0	0
T168	0	6	0	0
T169	0	224	0	0
T170	2890	0	0	0
T171	9041	0	0	0
T172	4484	0	0	0
T173	19071	0	0	0
T174	7465	0	0	0
T175	9470	0	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23423716	3045	0	0
T6	408916	0	0	0
T43	3750	0	0	0
T66	0	155	0	0
T67	0	210	0	0
T74	45372	59	0	0
T94	0	3	0	0
T95	0	35	0	0
T121	62145	0	0	0
T165	0	37	0	0
T166	0	33	0	0
T167	0	14	0	0
T168	0	3	0	0
T169	0	264	0	0
T170	2890	0	0	0
T171	9041	0	0	0
T172	4484	0	0	0
T173	19071	0	0	0
T174	7465	0	0	0
T175	9470	0	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23423716	3205	0	0
T6	408916	0	0	0
T43	3750	0	0	0
T66	0	103	0	0
T67	0	187	0	0
T74	45372	25	0	0
T95	0	32	0	0
T121	62145	0	0	0
T165	0	49	0	0
T166	0	36	0	0
T167	0	12	0	0
T168	0	5	0	0
T169	0	272	0	0
T170	2890	0	0	0
T171	9041	0	0	0
T172	4484	0	0	0
T173	19071	0	0	0
T174	7465	0	0	0
T175	9470	0	0	0
T176	0	151	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23423716	3208	0	0
T6	408916	0	0	0
T43	3750	0	0	0
T66	0	97	0	0
T74	45372	61	0	0
T94	0	3	0	0
T95	0	62	0	0
T121	62145	0	0	0
T165	0	28	0	0
T166	0	24	0	0
T167	0	15	0	0
T168	0	4	0	0
T169	0	283	0	0
T170	2890	0	0	0
T171	9041	0	0	0
T172	4484	0	0	0
T173	19071	0	0	0
T174	7465	0	0	0
T175	9470	0	0	0
T182	0	5	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23423716	3096	0	0
T6	408916	0	0	0
T43	3750	0	0	0
T66	0	103	0	0
T67	0	174	0	0
T74	45372	28	0	0
T94	0	10	0	0
T95	0	44	0	0
T121	62145	0	0	0
T165	0	32	0	0
T166	0	53	0	0
T167	0	27	0	0
T168	0	1	0	0
T169	0	211	0	0
T170	2890	0	0	0
T171	9041	0	0	0
T172	4484	0	0	0
T173	19071	0	0	0
T174	7465	0	0	0
T175	9470	0	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23423716	3107	0	0
T6	408916	0	0	0
T43	3750	0	0	0
T66	0	115	0	0
T67	0	242	0	0
T74	45372	23	0	0
T95	0	95	0	0
T121	62145	0	0	0
T165	0	22	0	0
T166	0	34	0	0
T167	0	13	0	0
T168	0	8	0	0
T169	0	247	0	0
T170	2890	0	0	0
T171	9041	0	0	0
T172	4484	0	0	0
T173	19071	0	0	0
T174	7465	0	0	0
T175	9470	0	0	0
T176	0	100	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23423716	3135	0	0
T6	408916	0	0	0
T43	3750	0	0	0
T66	0	103	0	0
T67	0	201	0	0
T74	45372	50	0	0
T94	0	5	0	0
T95	0	48	0	0
T121	62145	0	0	0
T165	0	14	0	0
T166	0	36	0	0
T167	0	5	0	0
T168	0	3	0	0
T169	0	231	0	0
T170	2890	0	0	0
T171	9041	0	0	0
T172	4484	0	0	0
T173	19071	0	0	0
T174	7465	0	0	0
T175	9470	0	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23423716	3059	0	0
T6	408916	0	0	0
T43	3750	0	0	0
T66	0	116	0	0
T67	0	204	0	0
T74	45372	38	0	0
T94	0	12	0	0
T95	0	26	0	0
T121	62145	0	0	0
T165	0	46	0	0
T166	0	25	0	0
T167	0	14	0	0
T168	0	5	0	0
T169	0	243	0	0
T170	2890	0	0	0
T171	9041	0	0	0
T172	4484	0	0	0
T173	19071	0	0	0
T174	7465	0	0	0
T175	9470	0	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23423716	3026	0	0
T6	408916	0	0	0
T43	3750	0	0	0
T66	0	106	0	0
T67	0	218	0	0
T74	45372	45	0	0
T95	0	82	0	0
T121	62145	0	0	0
T165	0	41	0	0
T166	0	22	0	0
T167	0	14	0	0
T168	0	5	0	0
T169	0	263	0	0
T170	2890	0	0	0
T171	9041	0	0	0
T172	4484	0	0	0
T173	19071	0	0	0
T174	7465	0	0	0
T175	9470	0	0	0
T176	0	123	0	0

sealing_sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23423716	2794	0	0
T6	408916	0	0	0
T43	3750	0	0	0
T66	0	117	0	0
T67	0	184	0	0
T74	45372	45	0	0
T94	0	5	0	0
T95	0	25	0	0
T121	62145	0	0	0
T165	0	55	0	0
T166	0	27	0	0
T167	0	23	0	0
T168	0	8	0	0
T169	0	221	0	0
T170	2890	0	0	0
T171	9041	0	0	0
T172	4484	0	0	0
T173	19071	0	0	0
T174	7465	0	0	0
T175	9470	0	0	0

sealing_sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23423716	3061	0	0
T6	408916	0	0	0
T43	3750	0	0	0
T66	0	129	0	0
T67	0	181	0	0
T74	45372	24	0	0
T94	0	1	0	0
T95	0	25	0	0
T121	62145	0	0	0
T165	0	58	0	0
T166	0	39	0	0
T167	0	14	0	0
T168	0	6	0	0
T169	0	283	0	0
T170	2890	0	0	0
T171	9041	0	0	0
T172	4484	0	0	0
T173	19071	0	0	0
T174	7465	0	0	0
T175	9470	0	0	0

sealing_sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23423716	2994	0	0
T6	408916	0	0	0
T43	3750	0	0	0
T66	0	101	0	0
T67	0	199	0	0
T74	45372	44	0	0
T94	0	3	0	0
T95	0	33	0	0
T121	62145	0	0	0
T165	0	42	0	0
T166	0	30	0	0
T167	0	26	0	0
T169	0	241	0	0
T170	2890	0	0	0
T171	9041	0	0	0
T172	4484	0	0	0
T173	19071	0	0	0
T174	7465	0	0	0
T175	9470	0	0	0
T176	0	136	0	0

sealing_sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23423716	2968	0	0
T6	408916	0	0	0
T43	3750	0	0	0
T66	0	120	0	0
T67	0	201	0	0
T74	45372	34	0	0
T95	0	47	0	0
T121	62145	0	0	0
T165	0	62	0	0
T166	0	52	0	0
T167	0	14	0	0
T168	0	8	0	0
T169	0	241	0	0
T170	2890	0	0	0
T171	9041	0	0	0
T172	4484	0	0	0
T173	19071	0	0	0
T174	7465	0	0	0
T175	9470	0	0	0
T176	0	156	0	0

sealing_sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23423716	2936	0	0
T6	408916	0	0	0
T43	3750	0	0	0
T66	0	105	0	0
T67	0	157	0	0
T74	45372	22	0	0
T94	0	13	0	0
T95	0	27	0	0
T121	62145	0	0	0
T165	0	25	0	0
T166	0	49	0	0
T167	0	9	0	0
T168	0	3	0	0
T169	0	220	0	0
T170	2890	0	0	0
T171	9041	0	0	0
T172	4484	0	0	0
T173	19071	0	0	0
T174	7465	0	0	0
T175	9470	0	0	0

sealing_sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23423716	3197	0	0
T6	408916	0	0	0
T43	3750	0	0	0
T66	0	143	0	0
T67	0	182	0	0
T74	45372	36	0	0
T94	0	7	0	0
T95	0	35	0	0
T121	62145	0	0	0
T165	0	48	0	0
T166	0	25	0	0
T167	0	15	0	0
T168	0	9	0	0
T169	0	224	0	0
T170	2890	0	0	0
T171	9041	0	0	0
T172	4484	0	0	0
T173	19071	0	0	0
T174	7465	0	0	0
T175	9470	0	0	0

sealing_sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23423716	3105	0	0
T6	408916	0	0	0
T43	3750	0	0	0
T66	0	103	0	0
T67	0	173	0	0
T74	45372	47	0	0
T94	0	6	0	0
T95	0	101	0	0
T121	62145	0	0	0
T165	0	34	0	0
T166	0	42	0	0
T167	0	17	0	0
T168	0	2	0	0
T169	0	251	0	0
T170	2890	0	0	0
T171	9041	0	0	0
T172	4484	0	0	0
T173	19071	0	0	0
T174	7465	0	0	0
T175	9470	0	0	0

sealing_sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23423716	3065	0	0
T6	408916	0	0	0
T43	3750	0	0	0
T66	0	90	0	0
T67	0	215	0	0
T74	45372	28	0	0
T94	0	5	0	0
T95	0	27	0	0
T121	62145	0	0	0
T165	0	38	0	0
T166	0	39	0	0
T167	0	20	0	0
T168	0	7	0	0
T169	0	237	0	0
T170	2890	0	0	0
T171	9041	0	0	0
T172	4484	0	0	0
T173	19071	0	0	0
T174	7465	0	0	0
T175	9470	0	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23423716	3063	0	0
T6	408916	0	0	0
T43	3750	0	0	0
T66	0	107	0	0
T67	0	183	0	0
T74	45372	28	0	0
T94	0	6	0	0
T95	0	37	0	0
T121	62145	0	0	0
T165	0	23	0	0
T166	0	19	0	0
T167	0	20	0	0
T168	0	1	0	0
T169	0	276	0	0
T170	2890	0	0	0
T171	9041	0	0	0
T172	4484	0	0	0
T173	19071	0	0	0
T174	7465	0	0	0
T175	9470	0	0	0