Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3210223	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

611423

1

T1

154

T2

161

T3

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3409006	1			T1	336		T2	602		T3	1
values[0x0]	204568	1			T1	46		T2	45		T3	8
values[0x1]	208072	1			T1	41		T2	39		T3	18

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2197009	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1624637

1

T1

216

T2

301

T3

13

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12889	1			T2	6		T16	4		T5	7
valid_sources[0x01]	11665	1			T2	2		T15	3		T16	2
valid_sources[0x02]	52045	1			T2	3		T15	8		T16	3
valid_sources[0x03]	12729	1			T2	1		T16	3		T5	2
valid_sources[0x04]	14900	1			T2	1		T16	1		T5	2
valid_sources[0x05]	11879	1			T2	1		T16	3		T5	1
valid_sources[0x06]	13027	1			T2	2		T15	3		T16	3
valid_sources[0x07]	14387	1			T2	3		T15	3		T16	5
valid_sources[0x08]	12094	1			T2	2		T16	1		T6	3
valid_sources[0x09]	12395	1			T2	3		T15	1		T16	2
valid_sources[0x0a]	14572	1			T2	2		T15	4		T16	3
valid_sources[0x0b]	12608	1			T2	2		T15	8		T16	5
valid_sources[0x0c]	14464	1			T2	2		T15	8		T16	3
valid_sources[0x0d]	12816	1			T2	4		T15	7		T16	1
valid_sources[0x0e]	12388	1			T2	3		T16	7		T5	1
valid_sources[0x0f]	12127	1			T2	1		T15	2		T16	2
valid_sources[0x10]	11744	1			T2	2		T15	1		T16	2
valid_sources[0x11]	21166	1			T2	1		T16	1		T5	3
valid_sources[0x12]	17071	1			T2	1		T15	4		T16	2
valid_sources[0x13]	15377	1			T16	2		T5	3		T6	1
valid_sources[0x14]	13688	1			T2	6		T15	3		T16	3
valid_sources[0x15]	18457	1			T2	6		T15	5		T16	6
valid_sources[0x16]	14326	1			T2	3		T16	6		T5	2
valid_sources[0x17]	13556	1			T2	2		T16	5		T5	3
valid_sources[0x18]	13113	1			T2	4		T15	11		T16	4
valid_sources[0x19]	13271	1			T2	3		T15	6		T16	3
valid_sources[0x1a]	18972	1			T2	1		T15	5		T16	2
valid_sources[0x1b]	11819	1			T2	3		T16	2		T5	2
valid_sources[0x1c]	14814	1			T16	5		T5	5		T38	2
valid_sources[0x1d]	13747	1			T2	4		T15	2		T16	4
valid_sources[0x1e]	29877	1			T2	1		T15	6		T16	2
valid_sources[0x1f]	12051	1			T2	3		T15	3		T16	4
valid_sources[0x20]	14478	1			T2	2		T16	6		T5	1
valid_sources[0x21]	25846	1			T2	4		T15	4		T16	3
valid_sources[0x22]	12156	1			T2	3		T16	1		T5	2
valid_sources[0x23]	16939	1			T2	4		T16	2		T6	1
valid_sources[0x24]	12484	1			T2	1		T3	1		T16	2
valid_sources[0x25]	46069	1			T2	5		T3	3		T16	1
valid_sources[0x26]	12157	1			T2	2		T15	1		T16	1
valid_sources[0x27]	53614	1			T2	4		T3	1		T16	6
valid_sources[0x28]	12865	1			T2	4		T15	1		T16	2
valid_sources[0x29]	12008	1			T2	3		T15	3		T16	1
valid_sources[0x2a]	12942	1			T2	1		T16	3		T5	3
valid_sources[0x2b]	11949	1			T2	5		T15	5		T16	5
valid_sources[0x2c]	12998	1			T2	2		T15	1		T16	2
valid_sources[0x2d]	18058	1			T2	3		T16	1		T5	2
valid_sources[0x2e]	13877	1			T2	1		T16	5		T5	6
valid_sources[0x2f]	12008	1			T2	5		T15	2		T16	1
valid_sources[0x30]	14091	1			T2	5		T16	5		T5	6
valid_sources[0x31]	16701	1			T2	4		T15	1		T16	4
valid_sources[0x32]	12089	1			T2	2		T15	9		T16	2
valid_sources[0x33]	12539	1			T2	2		T16	4		T5	2
valid_sources[0x34]	15958	1			T2	3		T15	2		T16	4
valid_sources[0x35]	12763	1			T2	3		T15	1		T16	1
valid_sources[0x36]	16736	1			T2	3		T15	3		T16	3
valid_sources[0x37]	15074	1			T16	6		T5	2		T6	1
valid_sources[0x38]	13443	1			T2	2		T16	1		T5	5
valid_sources[0x39]	22394	1			T2	1		T15	2		T5	4
valid_sources[0x3a]	11974	1			T2	6		T16	1		T17	8
valid_sources[0x3b]	12294	1			T2	2		T15	4		T5	2
valid_sources[0x3c]	12868	1			T2	1		T5	5		T6	2
valid_sources[0x3d]	12316	1			T2	2		T15	4		T16	2
valid_sources[0x3e]	11950	1			T2	3		T16	2		T5	4
valid_sources[0x3f]	13032	1			T2	5		T15	3		T16	1
valid_sources[0x40]	12861	1			T2	4		T16	2		T5	6
valid_sources[0x41]	12439	1			T2	2		T16	2		T5	2
valid_sources[0x42]	12102	1			T2	2		T15	10		T16	5
valid_sources[0x43]	12622	1			T2	4		T16	2		T5	2
valid_sources[0x44]	13494	1			T2	2		T16	5		T5	2
valid_sources[0x45]	12974	1			T2	4		T16	7		T5	3
valid_sources[0x46]	12252	1			T2	3		T15	10		T16	3
valid_sources[0x47]	15364	1			T2	6		T16	2		T5	1
valid_sources[0x48]	12152	1			T2	6		T16	2		T5	4
valid_sources[0x49]	12934	1			T16	3		T5	4		T38	1
valid_sources[0x4a]	11937	1			T2	1		T15	3		T5	4
valid_sources[0x4b]	12038	1			T2	2		T15	6		T16	2
valid_sources[0x4c]	14089	1			T2	5		T5	2		T6	19
valid_sources[0x4d]	11669	1			T2	1		T15	2		T16	1
valid_sources[0x4e]	11889	1			T2	4		T16	1		T5	3
valid_sources[0x4f]	12102	1			T2	1		T16	6		T5	2
valid_sources[0x50]	12497	1			T2	4		T16	5		T5	4
valid_sources[0x51]	16188	1			T15	4		T16	4		T5	7
valid_sources[0x52]	12321	1			T2	2		T15	1		T16	4
valid_sources[0x53]	12277	1			T2	1		T16	3		T5	3
valid_sources[0x54]	12448	1			T2	6		T15	2		T16	7
valid_sources[0x55]	15733	1			T2	2		T15	9		T16	3
valid_sources[0x56]	12026	1			T2	4		T16	3		T5	4
valid_sources[0x57]	13277	1			T2	5		T16	5		T5	1
valid_sources[0x58]	13133	1			T2	3		T15	6		T16	3
valid_sources[0x59]	19248	1			T2	3		T15	27		T16	1
valid_sources[0x5a]	12564	1			T2	4		T15	16		T16	5
valid_sources[0x5b]	13213	1			T2	2		T16	2		T5	3
valid_sources[0x5c]	13586	1			T2	3		T15	12		T16	3
valid_sources[0x5d]	15601	1			T2	5		T16	2		T5	7
valid_sources[0x5e]	12274	1			T2	1		T15	1		T5	3
valid_sources[0x5f]	12196	1			T15	3		T16	2		T5	5
valid_sources[0x60]	13668	1			T2	2		T16	10		T5	1
valid_sources[0x61]	12961	1			T2	2		T4	726		T15	8
valid_sources[0x62]	12569	1			T2	6		T16	1		T5	1
valid_sources[0x63]	13520	1			T2	3		T16	4		T5	3
valid_sources[0x64]	14405	1			T2	3		T15	8		T16	6
valid_sources[0x65]	13161	1			T2	2		T16	3		T5	5
valid_sources[0x66]	13422	1			T16	1		T5	2		T6	2
valid_sources[0x67]	11427	1			T2	1		T15	4		T16	2
valid_sources[0x68]	14518	1			T2	5		T6	4		T17	7
valid_sources[0x69]	12023	1			T2	3		T15	1		T16	1
valid_sources[0x6a]	16539	1			T2	2		T15	1		T16	5
valid_sources[0x6b]	12214	1			T2	4		T15	3		T16	2
valid_sources[0x6c]	13140	1			T2	1		T16	2		T5	3
valid_sources[0x6d]	11998	1			T2	4		T16	4		T5	1
valid_sources[0x6e]	13895	1			T2	3		T16	1		T5	2
valid_sources[0x6f]	16541	1			T2	4		T16	7		T5	2
valid_sources[0x70]	13893	1			T2	1		T16	2		T5	3
valid_sources[0x71]	11809	1			T16	5		T5	2		T6	5
valid_sources[0x72]	12418	1			T15	10		T16	4		T5	3
valid_sources[0x73]	13352	1			T2	1		T16	5		T5	1
valid_sources[0x74]	12586	1			T2	6		T15	11		T5	3
valid_sources[0x75]	11958	1			T15	1		T16	6		T5	3
valid_sources[0x76]	25110	1			T2	2		T16	4		T5	3
valid_sources[0x77]	12351	1			T2	3		T16	6		T5	3
valid_sources[0x78]	12326	1			T2	4		T15	1		T16	3
valid_sources[0x79]	14269	1			T2	2		T16	1		T5	5
valid_sources[0x7a]	12825	1			T2	1		T15	3		T16	4
valid_sources[0x7b]	12240	1			T2	3		T16	6		T5	1
valid_sources[0x7c]	12210	1			T15	3		T16	1		T5	2
valid_sources[0x7d]	13668	1			T3	2		T15	1		T16	5
valid_sources[0x7e]	15868	1			T2	5		T15	3		T16	3
valid_sources[0x7f]	12284	1			T2	2		T15	2		T16	4
valid_sources[0x80]	11939	1			T2	1		T15	5		T16	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

329508

1

T1

128

T2

135

T3

1

values[0x0]

all_enables

biggest_size

147708

1

T1

17

T2

17

T3

2

values[0x1]

all_enables

biggest_size

134207

1

T1

9

T2

9

T3

3