Unified Coverage Report :: Module :: keymgr_cfg_en

Module : keymgr_cfg_en

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr_cfg_en.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_cfgen	98.15	100.00	94.44			100.00
tb.dut.u_sw_binding_regwen	98.25	100.00	94.74			100.00

---

Module Instance : tb.dut.u_cfgen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.15	100.00	94.44			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.15	100.00	94.44			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.94	96.00	97.81	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sw_binding_regwen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.25	100.00	94.74			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.25	100.00	94.74			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.94	96.00	97.81	99.96		95.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : keymgr_cfg_en

	Line No.	Total	Covered	Percent
TOTAL		19	19	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	31	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	37	1	1	100.00
CONT_ASSIGN	38	1	1	100.00
ALWAYS	41	6	6	100.00
ALWAYS	52	8	8	100.00

29                      
30         1/1            assign vld_clr = init_q && clr_i;
           Tests:       T1 T2 T3 
31         1/1            assign vld_set = init_q && set_i;
           Tests:       T1 T2 T3 
32         1/1            assign vld_dis = init_q && !en_i;
           Tests:       T1 T2 T3 
33                      
34                        // the same cycle where clear is asserted should already block future
35                        // configuration
36                        logic out_clr;
37         1/1            assign out_clr = NonInitClr ? clr_i : vld_clr;
           Tests:       T1 T2 T3 
38         1/1            assign out_o = ~out_clr & out_q & en_i;
           Tests:       T1 T2 T3 
39                      
40                        always_ff @(posedge clk_i or negedge rst_ni) begin
41         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
42         1/1                init_q <= '0;
           Tests:       T1 T2 T3 
43         1/1              end else if (init_q && !en_i) begin
           Tests:       T1 T2 T3 
44         1/1                init_q <= '0;
           Tests:       T17 T18 T64 
45         1/1              end else if (init_i && en_i) begin
           Tests:       T1 T2 T3 
46         1/1                init_q <= 1'b1;
           Tests:       T1 T2 T3 
47                          end
                        MISSING_ELSE
48                        end
49                      
50                        // clearing the configure enable always has higher priority than setting
51                        always_ff @(posedge clk_i or negedge rst_ni) begin
52         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
53         1/1                out_q <= 1'b1;
           Tests:       T1 T2 T3 
54         1/1              end else if (vld_dis) begin
           Tests:       T1 T2 T3 
55         1/1                out_q <= 1'b0;
           Tests:       T17 T18 T64 
56         1/1              end else if (vld_set) begin
           Tests:       T1 T2 T3 
57         1/1                out_q <= 1'b1;
           Tests:       T1 T2 T4 
58         1/1              end else if (out_clr) begin
           Tests:       T1 T2 T3 
59         1/1                out_q <= 1'b0;
           Tests:       T1 T2 T4 
60                          end
                        MISSING_ELSE

---

Cond Coverage for Module : keymgr_cfg_en

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       30
 EXPRESSION (init_q && clr_i)
             ---1--    --2--

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T22
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       31
 EXPRESSION (init_q && set_i)
             ---1--    --2--

-1-	-2-	Status	Tests
0	1	Covered	T18,T64,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       32
 EXPRESSION (init_q && ((!en_i)))
             ---1--    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T17,T18,T64

 LINE       38
 EXPRESSION (((~out_clr)) & out_q & en_i)
             ------1-----   --2--   --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T16,T6,T17
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (init_q && ((!en_i)))
             ---1--    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T17,T18,T64

 LINE       45
 EXPRESSION (init_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : keymgr_cfg_en

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
IF	41	4	4	100.00
IF	52	5	5	100.00

41             if (!rst_ni) begin
               -1-  
42               init_q <= '0;
                 ==>
43             end else if (init_q && !en_i) begin
                        -2-  
44               init_q <= '0;
                 ==>
45             end else if (init_i && en_i) begin
                        -3-  
46               init_q <= 1'b1;
                 ==>
47             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T17,T18,T64
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

52             if (!rst_ni) begin
               -1-  
53               out_q <= 1'b1;
                 ==>
54             end else if (vld_dis) begin
                        -2-  
55               out_q <= 1'b0;
                 ==>
56             end else if (vld_set) begin
                        -3-  
57               out_q <= 1'b1;
                 ==>
58             end else if (out_clr) begin
                        -4-  
59               out_q <= 1'b0;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T17,T18,T64
0	0	1	-	Covered	T1,T2,T4
0	0	0	1	Covered	T1,T2,T4
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cfgen

	Line No.	Total	Covered	Percent
TOTAL		19	19	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	31	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	37	1	1	100.00
CONT_ASSIGN	38	1	1	100.00
ALWAYS	41	6	6	100.00
ALWAYS	52	8	8	100.00

29                      
30         1/1            assign vld_clr = init_q && clr_i;
           Tests:       T1 T2 T3 
31         1/1            assign vld_set = init_q && set_i;
           Tests:       T1 T2 T3 
32         1/1            assign vld_dis = init_q && !en_i;
           Tests:       T1 T2 T3 
33                      
34                        // the same cycle where clear is asserted should already block future
35                        // configuration
36                        logic out_clr;
37         1/1            assign out_clr = NonInitClr ? clr_i : vld_clr;
           Tests:       T1 T2 T3 
38         1/1            assign out_o = ~out_clr & out_q & en_i;
           Tests:       T1 T2 T3 
39                      
40                        always_ff @(posedge clk_i or negedge rst_ni) begin
41         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
42         1/1                init_q <= '0;
           Tests:       T1 T2 T3 
43         1/1              end else if (init_q && !en_i) begin
           Tests:       T1 T2 T3 
44         1/1                init_q <= '0;
           Tests:       T17 T18 T64 
45         1/1              end else if (init_i && en_i) begin
           Tests:       T1 T2 T3 
46         1/1                init_q <= 1'b1;
           Tests:       T1 T2 T3 
47                          end
                        MISSING_ELSE
48                        end
49                      
50                        // clearing the configure enable always has higher priority than setting
51                        always_ff @(posedge clk_i or negedge rst_ni) begin
52         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
53         1/1                out_q <= 1'b1;
           Tests:       T1 T2 T3 
54         1/1              end else if (vld_dis) begin
           Tests:       T1 T2 T3 
55         1/1                out_q <= 1'b0;
           Tests:       T17 T18 T64 
56         1/1              end else if (vld_set) begin
           Tests:       T1 T2 T3 
57         1/1                out_q <= 1'b1;
           Tests:       T1 T2 T4 
58         1/1              end else if (out_clr) begin
           Tests:       T1 T2 T3 
59         1/1                out_q <= 1'b0;
           Tests:       T1 T2 T4 
60                          end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_cfgen

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       30
 EXPRESSION (init_q && clr_i)
             ---1--    --2--

-1-	-2-	Status	Tests
0	1	Covered	T18,T64,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       31
 EXPRESSION (init_q && set_i)
             ---1--    --2--

-1-	-2-	Status	Tests
0	1	Covered	T18,T64,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       32
 EXPRESSION (init_q && ((!en_i)))
             ---1--    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T17,T18,T64

 LINE       38
 EXPRESSION (((~out_clr)) & out_q & en_i)
             ------1-----   --2--   --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Not Covered
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (init_q && ((!en_i)))
             ---1--    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T17,T18,T64

 LINE       45
 EXPRESSION (init_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_cfgen

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
IF	41	4	4	100.00
IF	52	5	5	100.00

41             if (!rst_ni) begin
               -1-  
42               init_q <= '0;
                 ==>
43             end else if (init_q && !en_i) begin
                        -2-  
44               init_q <= '0;
                 ==>
45             end else if (init_i && en_i) begin
                        -3-  
46               init_q <= 1'b1;
                 ==>
47             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T17,T18,T64
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

52             if (!rst_ni) begin
               -1-  
53               out_q <= 1'b1;
                 ==>
54             end else if (vld_dis) begin
                        -2-  
55               out_q <= 1'b0;
                 ==>
56             end else if (vld_set) begin
                        -3-  
57               out_q <= 1'b1;
                 ==>
58             end else if (out_clr) begin
                        -4-  
59               out_q <= 1'b0;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T17,T18,T64
0	0	1	-	Covered	T1,T2,T4
0	0	0	1	Covered	T1,T2,T4
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sw_binding_regwen

	Line No.	Total	Covered	Percent
TOTAL		19	19	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	31	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	37	1	1	100.00
CONT_ASSIGN	38	1	1	100.00
ALWAYS	41	6	6	100.00
ALWAYS	52	8	8	100.00

29                      
30         1/1            assign vld_clr = init_q && clr_i;
           Tests:       T1 T2 T3 
31         1/1            assign vld_set = init_q && set_i;
           Tests:       T1 T2 T3 
32         1/1            assign vld_dis = init_q && !en_i;
           Tests:       T1 T2 T3 
33                      
34                        // the same cycle where clear is asserted should already block future
35                        // configuration
36                        logic out_clr;
37         1/1            assign out_clr = NonInitClr ? clr_i : vld_clr;
           Tests:       T16 T6 T17 
38         1/1            assign out_o = ~out_clr & out_q & en_i;
           Tests:       T1 T2 T3 
39                      
40                        always_ff @(posedge clk_i or negedge rst_ni) begin
41         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
42         1/1                init_q <= '0;
           Tests:       T1 T2 T3 
43         1/1              end else if (init_q && !en_i) begin
           Tests:       T1 T2 T3 
44         1/1                init_q <= '0;
           Tests:       T17 T64 T68 
45         1/1              end else if (init_i && en_i) begin
           Tests:       T1 T2 T3 
46         1/1                init_q <= 1'b1;
           Tests:       T1 T2 T4 
47                          end
                        MISSING_ELSE
48                        end
49                      
50                        // clearing the configure enable always has higher priority than setting
51                        always_ff @(posedge clk_i or negedge rst_ni) begin
52         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
53         1/1                out_q <= 1'b1;
           Tests:       T1 T2 T3 
54         1/1              end else if (vld_dis) begin
           Tests:       T1 T2 T3 
55         1/1                out_q <= 1'b0;
           Tests:       T17 T64 T68 
56         1/1              end else if (vld_set) begin
           Tests:       T1 T2 T3 
57         1/1                out_q <= 1'b1;
           Tests:       T1 T2 T4 
58         1/1              end else if (out_clr) begin
           Tests:       T1 T2 T3 
59         1/1                out_q <= 1'b0;
           Tests:       T16 T6 T17 
60                          end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sw_binding_regwen

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       30
 EXPRESSION (init_q && clr_i)
             ---1--    --2--

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T22
1	0	Covered	T1,T2,T4
1	1	Covered	T16,T6,T17

 LINE       31
 EXPRESSION (init_q && set_i)
             ---1--    --2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       32
 EXPRESSION (init_q && ((!en_i)))
             ---1--    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T17,T64,T68

 LINE       38
 EXPRESSION (((~out_clr)) & out_q & en_i)
             ------1-----   --2--   --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T6,T17
1	0	1	Covered	T16,T6,T17
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (init_q && ((!en_i)))
             ---1--    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T17,T64,T68

 LINE       45
 EXPRESSION (init_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T18,T123,T124
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sw_binding_regwen

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
IF	41	4	4	100.00
IF	52	5	5	100.00

41             if (!rst_ni) begin
               -1-  
42               init_q <= '0;
                 ==>
43             end else if (init_q && !en_i) begin
                        -2-  
44               init_q <= '0;
                 ==>
45             end else if (init_i && en_i) begin
                        -3-  
46               init_q <= 1'b1;
                 ==>
47             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T17,T64,T68
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

52             if (!rst_ni) begin
               -1-  
53               out_q <= 1'b1;
                 ==>
54             end else if (vld_dis) begin
                        -2-  
55               out_q <= 1'b0;
                 ==>
56             end else if (vld_set) begin
                        -3-  
57               out_q <= 1'b1;
                 ==>
58             end else if (out_clr) begin
                        -4-  
59               out_q <= 1'b0;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T17,T64,T68
0	0	1	-	Covered	T1,T2,T4
0	0	0	1	Covered	T16,T6,T17
0	0	0	0	Covered	T1,T2,T3